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ZL50031 Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch
Data Sheet Features
* * * * * * * * * * * * * * * 4,096 x 2,048 blocking switching between backplane and local streams 2,048 x 2,048 non-blocking switching between local streams 2,048 x 2,048 non-blocking switching between backplane streams Rate conversion between backplane and local streams Backplane interface accepts data rates of 8.192 Mbps or 16.384 Mbps Local interface accepts data rates of 2.048 Mbps, 4.096 Mbps or 8.192 Mbps on a per group basis Meets all the key H.110 mandatory signal requirements including timing Per-channel variable or constant throughput delay Per-stream input delay, programmable for local streams on a per bit basis Per-stream output advancement, programmable for backplane and local streams Per-channel direction control for backplane streams Per-channel message mode for backplane and local streams Per-channel high impedance output control for backplane and local streams Compatible to Stratum 4 Enhanced clock switching standard Integrated PLL conforms to Telcordia GR-1244CORE Stratum 4 Enhanced switching standard * Holdover Mode with holdover frequency stability of 0.07 ppm Jitter attenuation from 1.52 Hz Time interval error (TIE) correction Master and Slave mode operation * * Ordering Information ZL50031QEG1 256 Pin HQFP* *Pb Free Matte Tin -40C to +85C Connection memory block-programming for fast device initialization Pseudo-Random Binary Sequence (PRBS) pattern generation and testing for backplane and local streams Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard 3.3 V operation with 5 V tolerant inputs and I/O's 5 V tolerant PCI driver on CT-Bus I/O's
February 2005
* * *
Applications
* * * * * * Carrier-grade VoIP Gateways IP-PBX and PABX Intregrated Access Devices Access Servers CTI Applications/CompactPCI(R) Platforms H.110, H.100, ST-BUS and proprietary Backplane Applications
Description
The ZL50031 Digital Switch provides switching capacities of 4,096 x 2,048 channels between backplane and local streams, 2,048 x 2,048 channels among local streams and 2,048 x 2,048 channels among backplane streams. The local connected serial inputs and outputs have 32, 64 and 128 64 kbps channels per frame with data rates of 2.048, 4.096 and 8.192 Mbps respectively. The backplane connected serial inputs and outputs have 128 and 256 64 kbps channels per frame with data rates of 8.192 and 16.384 Mbps respectively.
Non-multiplexed microprocessor interface
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912, France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved.
ZL50031
Data Sheet
The device has features that are programmable on a per-stream or a per-channel basis including message mode, input delay offset, output advancement offset, and direction control. The ZL50031 supports all three of the H.110 specification required clocking modes: Primary Master, Secondary Master and Slave.
VDD5V VDD VSS
PCI_OE ODE
BSTio0
Backplane Interface S/P & P/S Converter
Backplane Data Memory (4,096 channels) Output Mux
Local Interface P/S & P/S Converter
LSTi0
LSTi15
Local Connection Memory
(2,048 locations)
LSTo0
BSTio31 Output Mux
C20i
Local Data Memory (2,048 channels)
LSTo15
APLL
Backplane Connection Memory (4,096 locations)
Local Interface Timing Unit
ST_FPo0 ST_CKo0 ST_FPo1 ST_CKo1
RESET
DPLL
Internal Registers & Microprocessor Interface
Test Port
C8_A_io FRAME_A_io
C8_B_io FRAME_B_io
PRI_LOS SEC_LOS
LREF3-0
CTREF1 CTREF2
NREFo
C32/64o C1M5o
FAIL_A FAIL_B
Figure 1 - Functional Block Diagram
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DTA D15-D0
A13-A0
TMS TDi TDo TCK TRST
CS R/W
DS
ZL50031 Table of Contents
Data Sheet
1.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.0 Frame Alignment Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.0 Switching Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 Backplane Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 Local Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.0 Local Input Delay Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.0 Output Advancement Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.0 Local Output Timing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.0 Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.0 Delay Through the ZL50031 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.1 Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.2 Constant Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10.0 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10.1 DTA Data Transfer Acknowledgment Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11.0 Address Mapping of Memories and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 12.0 Backplane Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 13.0 Local Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 14.0 Bit Error Rate Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 15.0 DPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 15.1 ZL50031 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 15.1.1 Primary Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 15.1.2 Secondary Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 15.1.3 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 16.0 DPLL Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 16.1 Reference Select and Frequency Mode MUX Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 16.2 PRI and SEC MUX Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 16.3 Frame Select MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 16.4 CT Clock and Frame Monitor Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 16.5 Reference Monitor Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 16.6 State Machine Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 16.7 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 16.7.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 16.7.2 Holdover Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 16.7.3 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 17.0 Phase Locked Loop (PLL) Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 17.1 Skew Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 17.2 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 17.3 Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 17.4 Phase Offset Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 17.5 Phase Slope Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 17.6 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 17.7 Digitally Controlled Oscillator (DCO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 17.8 Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 17.9 Frequency Select MUX Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 18.0 Measures of Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 18.1 Intrinsic Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 18.2 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 18.3 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 18.4 Frequency Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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ZL50031 Table of Contents
Data Sheet
18.5 Holdover Frequency Stability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 18.6 Locking Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 18.7 Phase Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 18.8 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 18.9 Phase Lock Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 19.0 Initialization of the ZL50031 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 20.0 JTAG Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 20.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 20.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 20.3 Test Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 20.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 21.0 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 22.0 DC/AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 23.0 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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ZL50031 List of Figures
Data Sheet
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 1 - ZL50031 256-Pin 28 mm x 28 mm HQFP (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2 - CT-Bus Timing for 8 Mbps Backplane Data Streams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 3 - ST-BUS Timing for 16 Mbps Backplane Data Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4 - Block Programming Data in the Connection Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5 - Typical Timing Control Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 6 - DPLL Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 7 - State Machine Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 8 - Block Diagram of the PLL Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 9 - Skew Control Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 10 - DPLL Jitter Transfer Function Diagram - Wide Range of Frequencies . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 11 - Detailed DPLL Jitter Transfer Function Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 12 - Local Input Bit Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 13 - Example of Backplane Output Advancement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 14 - Local Output Advancement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 15 - Backplane Frame Pulse Input and Clock Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 16 - Backplane Frame Pulse Output and Clock Output Timing Diagram (in Primary Master Mode and Secondary Master Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 17 - Backplane Frame Pulse Input and Clock Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 18 - Reference Input Timing Diagram when the input frequency = 8 kHz . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 19 - Reference Input Timing Diagram when the input frequency = 2.048 MHz . . . . . . . . . . . . . . . . . . . . . 59 Figure 20 - Reference Input Timing Diagram when the input frequency = 1.544 Hz . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 21 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register . . . . . . . . . . . . . . . 60 Figure 22 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register . . . . . . . . . . . . . . . 60 Figure 23 - Reference Input Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register . . . . . . . . . . . . . . . . 60 Figure 24 - Reference Output Timing Diagram when (DIV1, DIV0) = (1, 0) in DOM2 Register . . . . . . . . . . . . . . . 60 Figure 25 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 1) in DOM2 Register . . . . . . . . . . . . . . . 61 Figure 26 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 4.096 MHz . . . . . . . . . . . . . . . . . . . . . . 61 Figure 27 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 8.192 MHz . . . . . . . . . . . . . . . . . . . . . . 62 Figure 28 - Local Clock Timing Diagram when ST_CKo frequency = 16.384 MHz . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 29 - C1M5o Output Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 30 - Backplane Serial Stream Timing when the Data Rate is 8 Mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 31 - Backplane Serial Stream Timing when the Data Rate is 16 Mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 32 - Local Serial Stream Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 33 - Local Serial Stream Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 34 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 35 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 36 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 37 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 38 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 39 - Reset Pin Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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ZL50031 List of Tables
Data Sheet
Table 1 - Mode Selection for Backplane Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 2 - Mode Selection for Local LSTi0 - 3 and LSTo0 - 3 Streams, Group 0. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3 - Mode Selection for Local LSTi4 - 7 and LSTo4 - 7 Streams, Group 1. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4 - Mode Selection for Local LSTi8 - 11 and LSTo8 - 11 Streams, Group 2 . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5 - Mode Selection for Local LSTi12 - 15 and LSTo12 - 15 Streams, Group 3. . . . . . . . . . . . . . . . . . . . . . . 15 Table 6 - Address Map For Internal Registers (A13 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 7 - Address Map for Memory Locations (A13 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 8 - Control Register (CR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 9 - Device Mode Selection (DMS) Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 10 - Block Programming Mode (BPM) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 11 - Local Input Bit Delay Registers (LIDR0 to LIDR5) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 12 - Local Input Bit Delay Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 13 - Backplane Output Advancement Registers (BOAR0 to BOAR3) Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 14 - Local Output Advancement Registers (LOAR0 to LOAR1) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 15 - Local Bit Error Rate Input Selection (LBIS) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 16 - Local Bit Error Rate Register (LBERR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 17 - Backplane Bit Error Rate Input Selection (BBIS) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 18 - Backplane Bit Error Rate Register (BBERR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 19 - DPLL Operation Mode (DOM1) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 20 - DPLL Operation Mode (DOM2) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 21 - ZL50031 Mode Selection - By Programming DOM1 and DOM2 Registers . . . . . . . . . . . . . . . . . . . . . 49 Table 22 - DPLL Output Adjustment (DPOA) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 23 - DPLL House Keeping (DHKR) Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 24 - Backplane Connection Memory Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 25 - BSAB and BCAB Bits Usage when Source Streams are from the Local Port. . . . . . . . . . . . . . . . . . . . 52 Table 26 - BSAB and BCAB Bits Usage when Source Streams are from the Backplane Port. . . . . . . . . . . . . . . . 52 Table 27 - Local Connection Memory Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 28 - LSAB and LCAB Bits Usage when Source Stream is from the Backplane Port . . . . . . . . . . . . . . . . . . 54 Table 29 - LSAB and LCAB Bits Usage when Source Stream is from the Local Port . . . . . . . . . . . . . . . . . . . . . . 54
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Zarlink Semiconductor Inc.
ZL50031
HQFP Pinout Diagram
Data Sheet
NC NC NC NC VDD5V VDD BSTio15 BSTio14 BSTio13 BSTio12 VSS VDD NC NC BSTio11 BSTio10 BSTio9 BSTio8 VSS VDD NC NC BSTio7 BSTio6 BSTio5 BSTio4 VSS VDD NC NC BSTio3 BSTio2 BSTio1 BSTio0 NC NC VDD5V VSS VDD NC DTA D15 D14 D13 D12 D11 D10 D9 D8 VSS VDD D7 D6 D5 D4 D3 D2 D1 D0 VSS VDD CS DS R/W
NC NC NC NC VSS VDD5V BSTio16 BSTio17 BSTio18 BSTio19 NC NC VDD VSS BSTio20 BSTio21 BSTio22 BSTio23 NC NC VDD VSS BSTio24 BSTio25 BSTio26 BSTio27 NC NC VDD VSS BSTio28 BSTio29 BSTio30 BSTio31 NC NC VDD VDD5V PCI_OEB LSTi0 LSTi1 LSTi2 LSTi3 LSTi4 LSTi5 LSTi6 LSTi7 VDD VSS LSTi8 LSTi9 LSTi10 LSTi11 LSTi12 LSTi13 LSTi14 LSTi15 VDD VSS IC_GND IC_GND IC_GND IC_GND IC_GND 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 156 154 152 150 148 146 144 142 140 138 136 134 132 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62
128 126 124 122 120 118 116 114 112 110 108 106 104 102
256 PIN HQFP (TOP VIEW)
100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64
IC_GND IC_GND IC_GND VSS IC_GND IC_GND IC_GND IC_GND VDD VSS NC LSTo0 LSTo1 LSTo2 LSTo3 VDD VSS LSTo4 LSTo5 LSTo6 LSTo7 VDD VSS LSTo8 LSTo9 LSTo10 LSTo11 VDD VSS LSTo12 LSTo13 LSTo14 LSTo15 VDD VSS NC NC NC NC VDD VSS NC NC NC NC NC NC NC NC ODE VDD VSS C8_A_io FRAME_A_io FAIL_A C8_B_io FRAME_B_io FAIL_B VDD VSS CTREF1 CTREF2 NREFo PRI_LOS
A13 A12 A11 A10 A9 A8 VSS VDD A7 A6 A5 A4 A3 A2 A1 A0 VSS VDD RESET TDo TMS TCK TRST TDi IC_GND IC_OPEN IC_OPEN IC_OPEN IC_OPEN ST_FPo1 ST_CKo1 IC_OPEN IC_OPEN IC_OPEN IC_OPEN VSS VDD IC_GND IC_GND IC_GND IC_OPEN IC_OPEN VSS APLLVDD APLLVSS C20i IC_GND VSS VDD IC_GND IC_GND IC_GND IC_GND LREF3 LREF2 LREF1 LREF0 C1M5o VSS ST_FPo0 ST_CKo0 VDD C32/64o SEC_LOS
Figure 1 - ZL50031 256-Pin 28 mm x 28 mm HQFP (top view)
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Zarlink Semiconductor Inc.
ZL50031
Pin Description
256 Pin HQFP 8,18,37,49 62,70,78,89,95 101,107,113,120 135,145,156,164 172,180,198,204 212,220,231,243 253 155,187,197,229 Name VDD +3.3 Volt Power Supply. Description
Data Sheet
VDD5V
+5.0 V/+3.3 V Power Supply. If 5 V power supply is tied to these pins, BSTio0-31 pins will meet 5 V PCI requirements. If 3.3 V power supply is tied to these pins, BSTio0-31 pins will meet 3.3 V PCI requirements. Ground.
7,17,36,43,48 59,69,77,88,94 100,106,112,119 125,134,144 163,171,179,188 203,211,219,230 242,252 44 45 19
VSS
APLLVDD APLLVSS RESET
+3.3 Volt Analog PLL Power Supply. No special filtering is required for this pin. Analog PLL Ground Device Reset (5 V Tolerant Input). This input (active low) puts the device in its reset state; this state clears the device's internal counters and registers. To ensure proper reset action, the reset pin must be low for longer than 400 ns. To ensure proper operation, a delay of 100 s must be applied before the first microprocessor access is performed after the RESET pin is set high. The device reset also tristates LSTo0-15 and BSTio0-31. When in a RESET condition, the C8_A_io, FRAME_A_io, C8_B_io, and FRAME_B_io signals are tri-stated. Backplane Serial Input/Output Streams 0 - 15 (5 V Tolerant PCI I/Os). In H.110 mode, these pins accept or output (selectable on a per channel basis) serial TDM data streams at 8.192 Mbps with 128 channels per stream. In the 16 Mbps mode, these pins accept serial TDM data streams at 16.384 Mbps with 256 channels per stream respectively. Backplane Serial Input/Output Streams 16 - 31 (5 V Tolerant PCI I/Os). In H.110 mode, these pins accept or output (selectable on a per channel basis) serial TDM data streams at 8.192 Mbps with 128 channels per stream. In the 16 Mbps mode, these pins are tristated internally and should be connected to ground. Local Serial Input Streams 0 to 3 (5 V Tolerant Inputs): In 2 Mb/s, 4 Mb/s or 8 Mb/s mode, these inputs accept data rates of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s with 32, 64 or 128 channels per stream respectively. Local Serial Input Streams 4 to 7 (5 V Tolerant Inputs): In 2 Mb/s, 4 Mb/s or 8 Mb/s mode, these inputs accept data rates of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s with 32, 64 or 128 channels per stream respectively.
226 to 223 218 to 215 210 to 207 202 to 199 186 to 183 178 to 175 170 to 167 162 to 159 153 to 150
BSTio0-3, BSTio4-7, BSTio8-11, BSTio12-15 BSTio16-19, BSTio20-23, BSTio24-27, BSTio28-31 LSTi0 - 3
149 to 146
LSTi4 - 7
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Zarlink Semiconductor Inc.
ZL50031
Pin Description (continued)
256 Pin HQFP 143 TO 140 Name LSTi8 - 11 Description
Data Sheet
Local Serial Input Streams 8 to 11 (5 V Tolerant Inputs): In 2 Mb/s, 4 Mb/s or 8 Mb/s mode, these inputs accept data rates of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s with 32, 64 or 128 channels per stream respectively. Local Serial Input Streams 12 to 15 (5 V Tolerant Inputs): In 2 Mb/s, 4 Mb/s or 8 Mb/s mode, these inputs accept data rates of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s with 32, 64 or 128 channels per stream respectively. Local Serial Output Streams 0 to 3 (5 V Tolerant Tri-state Outputs): In 2 Mb/s, 4 Mb/s or 8 Mb/s mode, these outputs have data rates of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s with 32, 64 or 128 channels per stream respectively. Local Serial Output Streams 4 to 7 (5 V Tolerant Tri-state Outputs): In 2 Mb/s, 4 Mb/s or 8 Mb/s mode, these outputs have data rates of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s with 32, 64 or 128 channels per stream respectively. Local Serial Output Streams 8 to 11 (5 V Tolerant Tri-state Outputs): In 2 Mb/s, 4 Mb/s or 8 Mb/s mode, these outputs have data rates of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s with 32, 64 or 128 channels per stream respectively. Local Serial Output Streams 12 to 15 (5 V Tolerant Tri-state Outputs): In 2 Mb/s, 4 Mb/s or 8 Mb/s mode, these outputs have data rates of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s with 32, 64 or 128 channels per stream respectively. Output Drive Enable (5 V Tolerant Input). When this pin is low, LSTo0-15, BSTio0-31, C1M5o, C32/64o, ST_CKo0, ST_CKo1, ST_FPo0 and ST_FPo1 outputs are all in high-impedance state. When ODE is high all of the aforementioned pins are active. Master Clock (5 V Tolerant Input). This pin accepts a 20.000 MHz clock. Clock A (5 V Tolerant I/O). This is an 8.192 MHz clock with 50% duty cycle.
139 to 136
LSTi12 - 15
117 to 114
LSTo0 - 3
111 to 108
LSTo4 - 7
105 to 102
LSTo8 - 11
99 to 96
LSTo12 - 15
79
ODE
46 76 75 73 72 74 71 68 67
C20i C8_A_io
FRAME_A_io Frame Reference A (5 V Tolerant I/O). This is a 122 ns wide, negative pulse, with 125 s period. C8_B_io Clock B (5 V Tolerant I/O). This is an 8.192 MHz clock with 50% duty cycle. FRAME_B_io Frame Reference B (5 V Tolerant I/O). This is a 122 ns wide, negative pulse, with 125 s period. FAIL_A FAIL_B CTREF1 CTREF2 A Failure (Output). When the C8_A_io or the FRAME_A_io signal fails, this signal goes to high. B Failure (Output). When the C8_B_io or the FRAME_B_io signal fails, this signal goes to high. CT-Bus Reference 1 (5 V Tolerant Input). This pin accepts 8 kHz, 1.544 MHz or 2.048 MHz network timing reference. CT-Bus Reference 2 (5 V Tolerant Input). This pin accepts 8 kHz, 1.544 MHz or 2.048 MHz network timing reference.
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Zarlink Semiconductor Inc.
ZL50031
Pin Description (continued)
256 Pin HQFP 57 to 54 66 Name LREF0 - 3 NREFo Description
Data Sheet
Local Reference (5 V Tolerant Inputs). These pins accept 8 kHz, 1.544 MHz or 2.048 MHz local timing reference. Network Reference Output (Output). Any local reference can be switched to this output. The output data rate can be either the same as the selected reference input data rate or divided to be 8 kHz. Primary Reference Lost (5 V Tolerant Input). When this signal is high, it indicates that PRIMARY REFERENCE is not valid. Combined with SEC_LOS input, this input pin is used in the External Reference Switching Mode of the DPLL. Secondary Reference Lost (5 V Tolerant Input). When this signal is high, it indicates that SECONDARY REFERENCE is not valid. Combined with the PRI_LOS input, this input pin is used in the External Reference Switching Mode of the DPLL. C32/64o Clock (5 V Tolerant Output). A 32.768 MHz output clock when the DPLL Clock Monitor register bit (CKM) is low. A 65.536 MHz clock when the DPLL Clock Monitor register bit (CKM) is high. C1.5o Clock (5 V Tolerant Output). A 1.544 MHz output clock. ST-BUS Frame Pulse Output (5 V Tolerant Output). The width of this output ST-BUS frame pulse can be 244 ns, 122 ns or 61 ns. The frequency is 8 kHz. ST-BUS Clock Output (5 V Tolerant Output). The frequency of this output ST-BUS clock can be 4.096 MHz, 8.192 MHz or 16.384 MHz. ST-BUS Frame Pulse Output (5 V Tolerant Output). The width of this output ST-BUS frame pulse can be 244 ns, 122 ns or 61 ns. The frequency is 8 kHz. ST-BUS Clock Output (5 V Tolerant Output). The frequency of this output ST-BUS clock can be 4.096 MHz, 8.192 MHz or 16.384 MHz. Chip Select (5 V Tolerant Input). This active low input is used by the microprocessor to access the microport. Data Strobe (5 V Tolerant Input). This active low input works in conjunction with CS to initiate the read and write cycles. Read/Write (5 V Tolerant Input). This input controls the direction of the data bus lines (D0 - D15) during the microprocessor access. Address 0 - 13 (5 V Tolerant Inputs). These are the address lines to the internal memories and registers. Data Bus 0 - 15 (5 V Tolerant I/Os). These pins form the 16-bit data bus of the microport. Data Transfer Acknowledge (5 V Tolerant Output). This active low output indicates that a data bus transfer is completed. A pull-up resistor is required to hold a high level.
65
PRI_LOS
64
SEC_LOS
63
C32/64o
58 60
C1M5o ST_FPo0
61 30
ST_CKo0 ST_FPo1
31 254 255 256 16 to 9 and 6 to 1 251 to 244 and 241 to 234 233
ST_CKo1 CS DS R/W A0 - A13
D0 - D15
DTA
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Zarlink Semiconductor Inc.
ZL50031
Pin Description (continued)
256 Pin HQFP 154 Name PCI_OE Description
Data Sheet
PCI Output Enable (3.3 V Tolerant Input). This active low input is the control signal used to tristate the BSTio0 - 31 pins during hot-swapping. During normal operation this signal should be low. Internal Connection. These pins MUST be connected to ground for normal operation.
25,38,39,40,47, 50,51,52,53,121, 122,123,124, 126,127,128,129, 130,131,132,133 26,27,28,29, 32,33,34,35, 41,42, 80 to 87, 90 to 93, 118,157,158,165, 166,173,174, 181,182, 189 to196 205,206,213,214, 221,222,227, 228,232 24
IC_GND
IC_OPEN
Internal Connection. These pins MUST be left open for normal operation.
NC
No Connection. These pins MUST be left unconnected for normal operation.
TDi
Test Serial Data In (3.3 V Input with Internal pull-up). JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up when not driven. Test Serial Data Out (3.3 V Tolerant Tri-state Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG is not enabled. Test Clock (5 V Tolerant Input). Provides the clock to the JTAG test logic. This pin should be low when JTAG is not enabled. Test Reset (3.3 V Input with Internal pull-up). Asynchronosly initializes the JTAG TAP Controller by putting it in the Test-Logic-Reset state. This pin should be pulled low to ensure that the ZL50031 is in normal functional mode. Test Mode Select (5 V Tolerant Input with Enabled Internal Pull-up): JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up resistor when it is not driven.
20
TDo
22 23
TCK TRST
21
TMS
11
Zarlink Semiconductor Inc.
ZL50031
1.0 Device Overview
Data Sheet
The ZL50031 can switch up to 4,096 x 2,048 channels while providing a rate conversion capability. It is designed to switch 64 kbps PCM or N X 64 kbps data between the backplane and local switching applications. The device maintains frame integrity in data applications and minimum throughput delay for voice applications on a perchannel basis. The backplane interface can operate at 8.192 Mbps in CT-Bus mode or 16.384 Mbps in ST-BUS mode and is arranged in 125 s wide frames that contain 128 or 256 channels respectively. A built-in rate conversion circuit allows users to interface between the backplane and the local interface which operates at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps. By using Zarlink's message mode capability, the microprocessor can access input and output time slots on a per channel basis. This feature is useful for transferring control and status information for external circuits or other TDM devices.
2.0
Functional Description
A Functional Block Diagram of the ZL50031 is shown in Figure 1 on page 2. It is designed to interface CT-Bus and ST-BUS serial streams from a backplane source and ST-BUS serial streams from a local source.
3.0
Frame Alignment Timing
In the ST-BUS or the CT-Bus mode, the C8_A_io or C8_B_io pin accepts an 8.192 MHz clock for the frame pulse alignment. The FRAME_A_io or FRAME_B_io is the frame pulse signal which goes low at the frame boundary for 122 ns. The frame boundary is defined by the rising edge of the C8_A_io or C8_B_io clock during the low cycle of the frame pulse. Figure 2 shows the CT-Bus timing for the backplane 8.192 Mbps data streams and Figure 3 shows the ST-BUS timing for the 16.384 Mbps backplane data streams.
FRAME_A_io, FRAME_B_io (CT Frame) C8_A_io, C8_B_io (8.192 MHz)
Channel 0 Channel 127 2 1 0 6 5 4 3 2 1 0 7
BSTio 0 - 31 (8 Mbps mode)
1
0
7
6
5
4
3
Figure 2 - CT-Bus Timing for 8 Mbps Backplane Data Streams
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Zarlink Semiconductor Inc.
ZL50031
FRAME_A_io, FRAME_B_io (CT Frame) C8_A_io, C8_B_io 8.192 MHz
Ch 255 Channel 0 Channel 1 Channel 254
Data Sheet
Channel 255
Ch 0
BSTio 0 - 15 (16 Mbps mode)
32107654321076543210
654321076543210765
Figure 3 - ST-BUS Timing for 16 Mbps Backplane Data Streams
4.0
Switching Configuration
The device has two operation modes at different data rates for the backplane interface and three operation modes for the local interface. These modes can be programmed via the Device Mode Selection (DMS) register. Mode selections between the backplane and local interfaces are independent.
4.1
Backplane Interface
The backplane interface can be programmed to accept data streams of 8 Mbps or 16 Mbps. When H.110 mode is enabled, BSTio0 to BSTio31 have a data rate of 8.192 Mbps. When ST-BUS mode is enabled, BSTio0 to BSTio15 have a data rate of 16.384 Mbps. Table 1 describes the data rates and mode selections for the backplane interface. BMS Bit of the DMS Register 0 1 Modes 8.192 Mbps 16.384 Mbps Table 1 - Mode Selection for Backplane Streams Backplane Interface BSTio0 - 31 BSTio0 - 15
4.2
Local Interface
The local side of the ZL50031 is divided up into 4 groups. Group 0 contains LSTi0-3 and LSTo0-3, Group 1 contains LSTi4-7 and LSTo4-7, Group 2 contains LSTi8-11 and LSTo8-11, Group 3 contains LSTi12-15 and LSTo12-15. Each group can be selected to operate in one of three data rates, 2.048 Mbps, 4.094 Mbps and 8.192 Mbps. The per-group data rate is selected through the Device Mode Selection (DMS) register. Streams belonging to the same group have the same operation at the same data rate. See Table 2 on page 14 for a description of the data rates and mode selection for the local ST-BUS interface.
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Zarlink Semiconductor Inc.
ZL50031
DMS Register Bits LG01 0 0 1 1 LG00 0 1 0 1
Data Sheet
Modes 8.192 Mbps 4.096 Mbps 2.048 Mbps Reserved
Usable Streams
LSTi0 - 3, LSTo0 - 3
Table 2 - Mode Selection for Local LSTi0 - 3 and LSTo0 - 3 Streams, Group 0
DMS Register Bits LG11 0 0 1 1 LG10 0 1 0 1
Modes 8.192 Mbps 4.096 Mbps 2.048 Mbps Reserved
Usable Streams
LSTi4 - 7, LSTo4 - 7
Table 3 - Mode Selection for Local LSTi4 - 7 and LSTo4 - 7 Streams, Group 1
DMS Register Bits LG21 0 0 1 1 LG20 0 1 0 1
Modes 8.192 Mbps 4.096 Mbps 2.048 Mbps Reserved
Usable Streams
LSTi8 - 11, LSTo8 - 11
Table 4 - Mode Selection for Local LSTi8 - 11 and LSTo8 - 11 Streams, Group 2
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Zarlink Semiconductor Inc.
ZL50031
DMS Register Bits LG31 0 0 1 1 LG30 0 1 0 1
Data Sheet
Modes 8.192 Mbps 4.096 Mbps 2.048 Mbps Reserved
Usable Streams
LSTi12-15, LSTo12-15
Table 5 - Mode Selection for Local LSTi12 - 15 and LSTo12 - 15 Streams, Group 3
5.0
Local Input Delay Selection
The local input delay selection allows individual local input streams to be aligned and shifted against the input frame pulse (FRAME_A_io or FRAME_B_io). This feature compensates for the variable path delays in the local interface. Such delays can occur in large centralized and distributed switching systems. Each local input stream can have its own bit delay offset value by programming the local input bit delay selection registers (LIDR0 to LIDR5). See Table 11, "Local Input Bit Delay Registers (LIDR0 to LIDR5) Bits" on page 39, for the contents of these registers. Possible bit adjustment can range up to +7 3/4 bit periods forward with resolution of 1/4 bit period. See Table 12 on page 39 and Figure 12 on page 40 for local input delay programming.
6.0
Output Advancement Selection
The ZL50031 allows users to advance individual backplane or local output streams with respect to the frame boundary. This feature is useful in compensating for variable output delays caused by various output loading conditions. Each output stream can have its own advancement value programmed by the output advancement registers. The backplane output advancement registers (BOAR0 to BOAR3) are used to program the backplane output advancement. The local output advancement registers (LOAR0 to LOAR1) are used to program the local output advancement. Possible adjustment for local and backplane output data streams is 22.5 ns with a resolution of 7.5 ns. The advancement is independent of the output data rate. Table 13 on page 41 and Figure 13, "Example of Backplane Output Advancement Timing" on page 41, and Table 14 on page 42 and Figure 14, "Local Output Advancement Timing" on page 42 describe the details of the output advancement programming for the backplane and local interfaces respectively.
7.0
Local Output Timing Considerations
The output data of the ZL50031's local side is slightly advanced with respect to the frame and bit boundary as defined by the local output clocks and frame pulses (ST_FPo0, ST_CKo0, ST_FPo1, ST_CKo1). The advancement is in the range of 5 ns to 17 ns. Despite this advancement, the ZL50031 will operate within the parameters specified in the datasheet because input data are usually sampled at the 3/4 or 1/2 point of the bit cell. However, the user should be cautious when introducing additional delay to the clock signals only (e.g., by passing them through glue logic, FPGA, or CPLD), which will introduce a few nanoseconds of delay relative to the data. If the clock signal is delayed, data will be advanced from the receiver device's point of view. This may cause errors in sampling the data. Using an example where a 3/4 sampling point is used, there is about 30 ns from the sampling point to the end of the bit cell. With a worst-case of 17 ns advancement, the timing margin will be approximately 13 ns. Any additional delays applied to the local output clocks (ST_CKo0 and ST_CKo1) must not exceed 13 ns minus the hold time of the receiving device. Delays applied to both clocks and data equally will not impact the device operation.
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Zarlink Semiconductor Inc.
ZL50031
8.0 Memory Block Programming
Data Sheet
The ZL50031 block programming mode (BPM) register provides users with the capability of initializing the local and backplane connection memories in two frames. Bit 13 - bit 15 of every backplane connection memory location will be programmed with the pattern stored in bit 6 - bit 8 of the BPM register. Bit 13 - bit 15 of every local connection memory location will be programmed with the pattern stored in bits 3 to 5 of the BPM register. The other bit positions of the backplane connection memory and the local connection memory are loaded with zeros. See Figure 4 on page 16 for the connection memory contents when the device is in block programming mode. The block programming mode is enabled by setting the memory block program (MBP) bit of the Control Register to high. After the block programming enable (BPE) bit of the BPM register is set to high, the block programming data will be loaded into bits 13 to 15 of every backplane connection memory location and bits 13 to 15 of every local connection memory low location. The other connection memory bits are loaded with zeros. When the memory block programming is completed, the device resets the BPE bit to low. See Table 10 on page 37 for the bit assignment of the BPM register.
15 14 13 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
BBPD2 BBPD1 BBPD0
Backplane Connection Memory (BCM)
15 14 13 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
LBPD2 LBPD1 LBPD0
Local Connection Memory (LCM)
Figure 4 - Block Programming Data in the Connection Memories
9.0
Delay Through the ZL50031
The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform time slot interchange functions with different throughput delay capabilities on a per-channel basis. For voice applications it is recommended to select variable throughput delay to ensure minimum delay between input and output data. In wideband data applications it is recommended to select constant throughput delay to maintain the frame integrity of the information through the switch. The delay through the device varies according to the type of throughput delay selected in the BTM2 - BTM0 bits of the backplane connection memory or LTM0 - LTM2 bits of the local connection memory as described in Table 24 on page 51 and Table 27 on page 53, respectively.
9.1
Variable Delay Mode
The delay in this mode is dependent only on the combination of source and destination channels and is independent of input and output streams. The minimum delays achievable in the ZL50031 device are 3-channel delay, 5-channel delay, and 10-channel delay for the 2 Mbps, 4 Mbps, and 8 Mbps data rates respectively. The maximum delay is one frame plus 3 channels, one frame plus 5 channels, and one frame plus 10 channels for the 2 Mbps, 4 Mbps and 8 Mbps modes respectively. For the backplane interface, the variable delay mode can be programmed through the backplane connection memory bits, BTM2 - BTM0. When BTM2 - BTM0 are programmed to "000", it is a per-channel variable delay from local input to the backplane output. When BTM2 - BTM0 are set to "010", it is a per-channel variable delay from backplane input to backplane output.
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Data Sheet
For the local interface, the variable delay mode can be programmed through the local connection memory low bits, LTM2 - LTM0. When LTM2 - LTM0 are programmed to "000", it is a per-channel variable delay from local input to local output. When LTM2 - LTM0 are set to "010", it is a per-channel variable delay from backplane input to local output.
9.2
Constant Delay Mode
In this mode, a multiple page data memory buffer is used to maintain frame integrity in all switching configurations such that a channel written during frame N is always read out during frame N+2. For the backplane interface, when BTM2 - BTM0 are programmed to "001", it is a per-channel constant delay mode from local input to backplane output. When BTM2 - BTM0 are programmed to "011", it is a per-channel constant delay from backplane input to backplane output. For the local interface, when LTM2 - LTM0 are programmed to "001", it is a per-channel constant delay mode from local input to local output. When LTM2 - LTM0 are set to "011", it is a per-channel constant delay mode from backplane input to local output.
10.0
Microprocessor Interface
The ZL50031 provides a parallel microprocessor interface for non-multiplexed bus structures. This interface is compatible with Motorola non-multiplexed bus structures. The required microprocessor signals are the 16-bit data bus (D15-D0), 14-bit address bus (A13-A0) and 4 control lines (CS, DS, R/W and DTA). See Figure 37, "Motorola Non-Multiplexed Bus Timing" on page 71 for the Motorola non-multiplexed bus timing. The ZL50031 microprocessor port provides access to the internal registers, the connection and data memories. All locations provide read/write access except for the Local and Backplane Bit Error Rate registers (LBERR and BBERR) and Data Memory which can only be read by the users.
10.1
DTA Data Transfer Acknowledgment Pin
The DTA pin of the microprocessor is driven LOW by internal logic to indicate that a data bus transfer is completed. When the bus cycle ends, this pin switches to the high impedance state. An external pull-up of between 1 k and 10 k is required at this output.
11.0
Address Mapping of Memories and Registers
The address bus on the microprocessor interface selects the internal registers and memories of the ZL50031. If the address bit A13 is low, the registers are addressed by A12 to A0 as shown in Table 6 on page 17. A13 - A0 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H Control Register, CR Device Mode Selection Register, DMS Block Programming Mode Register, BPM Reserved Local Input Bit Delay Register 0, LIDR0 Local Input Bit Delay Register 1, LIDR1 Local Input Bit Delay Register 2, LIDR2 Local Input Bit Delay Register 3, LIDR3 Location
Table 6 - Address Map For Internal Registers (A13 = 0)
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Zarlink Semiconductor Inc.
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A13 - A0 0008H 0009H 000AH to 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H to 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH Location Local Input Bit Delay Register 4, LIDR4 Local Input Bit Delay Register 5, LIDR5 Reserved Backplane Output Advancement Register 0, BOAR0 Backplane Output Advancement Register 1, BOAR1 Backplane Output Advancement Register 2, BOAR2 Backplane Output Advancement Register 3, BOAR3 Local Output Advancement Register 0, LOAR0 Local Output Advancement Register 1, LOAR1 Reserved Local BER Input Selection Register, LBIS Local BER Register, LBERR Backplane BER Input Selection Register, BBIS Backplane BER Register, BBERR DPLL Operation Mode Register 1, DOM1 DPLL Operation Mode Register 2, DOM2 DPLL Output Adjustment Register, DPOA DPLL House Keeping Register, DHKR
Data Sheet
Table 6 - Address Map For Internal Registers (A13 = 0) (continued) If A13 is high, the remaining address input lines are used to select the data and connection memory positions corresponding to the serial input or output data streams as shown in Table 7 on page 19. The Control register (CR), the Device Mode Selection register (DMS) and the Block Programming Mode register (BPM) control all the major functions of the device. The DMS and BPM should be programmed immediately after system power up to establish the desired switching configuration. The Control register is used to select Data or Connection Memory for microport operations, ST-BUS output frame and clock modes, and to set Memory Block Programing and Bit Error Rate Testing. The Control register (CR) consists of the memory block programming bit (MBP) and the memory select bits (MS20). The memory block programming bit allows users to program the entire connection memory in two frames (See Section 8.0, "Memory Block Programming" on page 16). The memory select bits control the selection of the connection memories or the data memories. See Table 8 on page 35 for contents of the Control register. The DMS register consists of the backplane and the local mode selection bits (BMS, LG31 - LG30, LG21 - LG20, LG11 - LG10 and LG01 - LG00) that are used to enable various switching modes for the backplane and the local interfaces respectively. See Table 9 on page 36 for the content of the DMS register. The BPM register consists of the block programming data bits (LBPD2-0 and BBPD2-0) and the block programming enable bit (BPE). The block programming enable bit allows users to program the entire backplane and local connection memories in two frames (see section 8.0, "Memory Block Programming" on page 16). If the ODE pin is low, the backplane CT-Bus is in input mode and the local output drivers are in high impedance state. If the ODE pin
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Data Sheet
is high, all the backplane CT-Bus and local ST-BUS I/O drivers are controlled on a per-channel basis by backplane and local connection memories, respectively. By programming BTM2-0 bits to "110" in the backplane connection memory, the user can control the per-channel input (can be used for high impedance) on the backplane interface. For the local interface, users can program LTM2 -0 bits to "110" in the local connection memory to control the perchannel input (can be used for high impedance). See Table 10 on page 37 for the content of the BPM register.
A13 (Note 1) 1 1 1 1 1 1 1 1 1 . . . . . . . 1 1 1 1 1 Stream Address (ST0-31) A12 0 0 0 0 0 0 0 0 0 . . 0 . . . . 1 1 1 1 1 A11 0 0 0 0 0 0 0 0 1 . . 1. . . . . 1 1 1 1 1 A10 0 0 0 0 1 1 1 1 0 . . 1 . . . . 0 1 1 1 1 A9 0 0 1 1 0 0 1 1 0 . . 1 . . . . 1 0 0 1 1 A8 0 1 0 1 0 1 0 1 0 . . 1 . . . . 1 0 1 0 1 Stream # Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7 Stream 8 . . Stream 15 (Note 6). . . . Stream 27 Stream 28 Stream 29 Stream 30 Stream 31 A7 0 0 . . 0 0 0 0 . . 0 0 . . 0 0 . . . 1 1 A6 0 0 . . 0 0 0 0 . . 0 0 . . 1 1 . . . 1 1 A5 0 0 . . 0 0 1 1 . . 1 1 . . 1 1 . . . 1 1 A4 0 0 . . 1 1 0 0 . . 1 1 . . 1 1 . . 1 1 Channel Address (Ch0-255) A3 0 0 . . 1 1 0 0 . . 1 1 . . 1 1 . . . 1 1 A2 0 0 . . 1 1 0 0 . . 1 1 . . 1 1 . . . 1 1 A1 0 0 . . 1 1 0 0 . . 1 1 . . 1 1 . . . 1 1 A0 0 1 . . 0 1 0 1 . . 0 1 . . 0 1 . . . 0 1 Channel # Ch 0 Ch 1 . . Ch 30 Ch 31 (Note 2) Ch 32 Ch 33 . . Ch 62 Ch 63 (Note 3) . . Ch 126 Ch 127 (Note 4) . . . Ch 254 Ch 255 (Note 5)
Notes: 1. A13 must be high for access to data and connection memory positions. A13 must be low for access to registers. 2. Channels 0 to 31 are used when serial stream is at 2 Mbps. 3. Channels 0 to 63 are used when serial stream is at 4 Mbps. 4. Channels 0 to 127 are used when serial stream is at 8 Mbps. 5. Channels 0 to 255 are used when serial stream is at 16 Mbps. 6. The local side uses Streams 0 to 15 only while the backplane uses streams 0 to 31.
Table 7 - Address Map for Memory Locations (A13 = 1)
12.0
Backplane Connection Memory
The backplane connection memory controls the switching configuration of the backplane interface. Locations in the backplane connection memory are associated with particular BSTio streams. The BTM2 - 0 bits of each backplane connection memory entry allow the per-channel selection from message mode, connection mode, constant delay, variable delay or bit error test mode. The backplane connection memory is also where the BSTio channels are set to be either inputs or outputs. See Table 24 on page 51 for the per-channel control functions. In the switching mode, the contents of the backplane connection memory stream address bits (BSAB4-0) and channel address bits (BCAB7-0) define the source information (stream and channel) of the time slot that will be switched to the backplane BSTio streams. During message mode, the 8 least significant bits of the backplane connection memory will be transferred to the BSTio pins.
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13.0 Local Connection Memory
Data Sheet
The local connection memory controls the local interface switching configuration. Locations in the local connection memory are associated with particular LSTo streams. The LTM2 - 0 bits of each local connection memory entry allow the per-channel selection from message mode, connection mode, constant delay, variable delay or bit error test mode. See Table 27 on page 53 for the perchannel control functions. In the switching mode, the contents of the local connection memory stream address bits (LSAB4-0) and the channel address bits (LCAB7-0) define the source information (stream and channel) of the time slot that will be switched to the local LSTo streams. During message mode, only the 8 least significant bits of the local connection memory low bits are transferred to the LSTo pins.
14.0
Bit Error Rate Test
The ZL50031 offers users a Bit Error Rate (BER) test feature for the backplane and the local interfaces. The circuitry of the BER test consists of a transmitter and a receiver on both interfaces that can transmit and receive the BER patterns independently. The transmitter can output a pseudo-random pattern of the form 215 - 1 to any channel and any stream within a frame. For the test, users can program the output channel and stream through the backplane or local connection memory and the input channel and stream using Local or Backplane BER Input Selection (BIS) registers. See Table 15 on page 43 and Table 17 on page 43 for the LBIS and the BBIS registers contents, respectively. The receiver receives the BER pattern and does an internal BER pattern comparison. For backplane interface, the comparison result is stored in the Backplane BER register (BBERR). For local interface, the result is stored in the Local BER register (LBERR).
15.0
DPLL
The Digital Phase Locked Loop (DPLL) accepts selectable 2.048 MHz, 1.544 MHz or 8 kHz input reference signals. It accepts reference inputs from independent sources and provides bit-error-free reference switching. The DPLL meets phase slope and MTIE requirements defined by the Telcordia GR-1244-CORE standard. The DPLL also provides the timing for the rest of the ZL50031 Digital Switch, generating several network clocks with the appropriate quality. Clocks are synchronized to one of two input reference clocks and meet the requirements of the H.110 clock specification.
15.1
ZL50031 Modes of Operation
The DPLL, and consequently the ZL50031, can, as required by the H.110 standard, operate in three different modes: Primary Master, Secondary Master and Slave. See Figure 5, "Typical Timing Control Configuration" on page 21. To configure the DPLL, there are two Operation Mode registers: DOM1 and DOM2. See Table 19 on page 44 and Table 20 on page 47 for the contents of these registers. In all modes the ZL50031 monitors both the "A Clocks" (C8_A_io and FRAME_A_io) and the "B Clocks" (C8_B_io and FRAME_B_io). The Fail_A and the Fail_B signals indicate the quality of the "A Clocks" and "B Clocks" respectively.
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CT_C8_A/CT_FRAME_A CT_C8_B/CT_FRAME_B CT_NETREF1 CT_NETREF2
Data Sheet
NREFo
A_Clocks
A_Clocks
B_Clocks
B_Clocks
CTREF1
CTREF2
CTREF1
CTREF2
A_Clocks
B_Clocks
A_Clocks
LREF0-3 PRIMARY MASTER Network Ref (8 kHz / T1 / E1)
LREF0-3 SECONDARY MASTER Network Ref (8 kHz / T1 / E1)
LREF0-3 SLAVE
LREF0-3 SLAVE
Network Ref (8 kHz / T1 / E1)
Network Ref (8 kHz / T1 / E1)
Figure 5 - Typical Timing Control Configuration
15.1.1
Primary Master Mode
In the Primary Master Mode, the ZL50031 drives the "A Clocks" (C8_A_io and FRAME_A_io), by locking to the primary reference (PRI_REF). The PRI_REF can be provided by one of the locally derived network reference sources (LREF0-3), the CTREF1 input or the CTREF2 input. In this mode the ZL50031 has the ability to monitor the primary reference. If the primary reference becomes unreliable, the device continues driving "A Clocks" in stable Holdover Mode until it makes a Stratum 4 Enhanced compatible switch to the secondary reference (SEC_REF) for its network timing. The secondary reference can be provided by one of the local network references (LREF0-3), CTREF1 or CTREF2. If the primary reference comes back or recovers, the ZL50031 makes a Stratum 4 Enhanced compatible switch back to the original primary reference and the system returns to normal operation state. If necessary, the ZL50031 can be prevented from switching back to the original primary reference by programming the RPS bit in DOM1 register to give preference to the secondary reference. While in the Primary Master mode, the ZL50031 attenuates jitter and wander above 1.52 Hz from the selected input reference clock and generates all output clocks according to the DPLL jitter transfer function diagram on Figure 10 on page 31 and Figure 11 on page 32. For the Primary Master mode selection, see Table 21, "ZL50031 Mode Selection - By Programming DOM1 and DOM2 Registers" on page 49.
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Zarlink Semiconductor Inc.
B_Clocks
NREFo
ZL50031
15.1.2 Secondary Master Mode
Data Sheet
In the Secondary Master Mode, the ZL50031 drives the "B Clocks" (C8_B_io and FRAME_B_io), by locking to the "A Clocks". As required by the H.110 standard, the "B Clocks" are edge-synchronous with the "A Clocks", as long as jitter on the "A Clocks" meets Telcordia GR-1244-CORE specifications. If the "A Clocks" become unreliable, system software is notified and the ZL50031 continues driving the "B Clocks" in stable Holdover Mode until it makes a Stratum 4 Enhanced compatible switch to the secondary reference (SEC_REF) for its network timing. The secondary reference can be a local network reference (LREF0-3), CTREF1 or CTREF2. If the "A Clocks" cannot recover, the designated secondary master can be promoted to primary master by system software. This promotion will cause the "B Clocks" to assume the role of the "A Clocks". For the Secondary Master mode selection, see Table 21, "ZL50031 Mode Selection - By Programming DOM1 and DOM2 Registers" on page 49.
15.1.3
Slave Mode
In the Slave Mode, the ZL50031 is phase locked to the "A Clocks". If the "A Clocks" become unreliable, the device goes to stable Holdover Mode until it makes a Stratum 4 Enhanced compatible switch to the "B Clocks". The ZL50031 will perform all required functionality as long as the "A Clocks" and the "B Clocks" conform to the Telcordia GR-1244-CORE jitter specifications. In addition, the device can be used to generate a NREFo reference from its network references, LREF0-3. In most systems NREFo is connected to either CT_REF1 or CT_REF2. While the device is in Slave Mode and the "A Clocks" or the "B Clocks" do not recover, the designated slave can be promoted to secondary master by system software. In that case, the network reference can be used as the secondary reference. Table 21 on page 49 shows how to program the DOM1 and DOM2 registers to enable the Slave Mode of the ZL50031.
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16.0 DPLL Functional Description
HOLDOVER_RESET
Data Sheet
(HRST bit in DOM2)
(POS0-6 bits in DPOA) (MRST bit in DOM2)
PHASE_OFFSET
MTIE_RESET
SKEW_CONTROL
(SK0-2 bits in DPOA)
(RPS bit in DOM1)
REF_SEL PRI MUX
LOS_PRI
PRI_LOS Pin
C32/64
HOLDOVER MTIE_START MTIE_DONE
(Selected by FDM0-1 bits in DOM2)
AUTODETECT
State Machine (Fig 6) SEC MUX
LOS_SEC
CT_C8 (C8_A_o) PLL (Fig 8) (C8_B_o) C1M5o CT_FRAME (FRAME_A_o)
or or
SEC_LOS Pin
REF_SELECT
FREQ_MOD_PRI
(FP1-0 bits in DOM1)
(FRAME_B_o)
Frequency
FREQ_MOD_SEC
(FS1-0 bits in DOM1)
Mode
MUX
FREQ_MOD
PRI_REF
(Selected by SP3-0 bits in DOM1)
SEC_REF
(Selected by SS3-0 bits in DOM1)
Reference Select MUX
REF
FRAME
Primary ref fail
Reference Monitor
C8_A_i FRAME_A_i FRAME_B_i Frame Select MUX
CT Clock and Frame Monitor
FAIL_A
CLK80M
Reference Secondary ref fail Monitor
C8_B_i
CT Clock and Frame Monitor
FAIL_B
C20i
APLL
Figure 6 - DPLL Functional Block Diagram
16.1
Reference Select and Frequency Mode MUX Circuits
The DPLL accepts two simultaneous reference input signals and operates on their rising edges. Either the primary reference (PRI_REF) signal or the secondary reference (SEC_REF) signal can be selected to be the reference signal (REF) to the PLL circuit. The appropriate frequency mode input (either FREQ_MOD_PRI or FREQ_MOD_SEC) is selected to be the input of the PLL circuit. The selection is done by the State Machine Circuit based on the current state. The FREQ_MOD_PRI and the FREQ_MOD_SEC are 2-bit wide inputs which reflect the value in the FP1-0 and FS1-0 bits of the DOM1 register. The primary and the secondary references operate independently from each other and can have different frequencies. Switching the reference from one frequency to another does not require the device reset to be applied. Table 19 on page 44 shows input frequency selection for the primary and secondary reference respectively.
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16.2 PRI and SEC MUX Circuits
Data Sheet
The DPLL has four different modes to handle reference failure. These modes are selected by the FDM0 and FDM1 bits of the DOM2 Register. If FDM1-0 is '10' then the Primary reference is always used regardless of failures. If FDM1-0 is '11' then the Secondary reference is always used regardless of failures. Otherwise the DPLL operates in one of two failure detection modes: Autodetect or Manual detection mode. When the FDM0 and FDM1 bits are set to low in the DOM2 register (`00'), the DPLL is in the Autodetect Mode. In this mode, the outputs from the Reference Monitor Circuits LOS_PRI and LOS_SEC are used by the State Machine Circuit. When the FDM0 bit is set to high and FDM1 bit is set to low (`01'), the DPLL is in the Manual Detection Mode and the LOS_PRI and LOS_SEC signals are selected from the PRI_LOS and SEC_LOS input pins to be used by the State Machine Circuit. See Table 20 on page 47 for selection of the Failure Detection Modes.
16.3
Frame Select MUX
When the "A Clocks" or the "B Clocks" are selected as the input reference, an 8.192 MHz clock (either C8_A_io or C8_B_io) is provided to be the input reference to the PLL circuit. Because the output frame pulse (CT_FRAME) must be aligned with the selected input frame pulse, the appropriate frame pulse (either FRAME_A_io or FRAME_B_io) is selected in the Frame Select MUX circuit to be the input of the PLL circuit.
16.4
CT Clock and Frame Monitor Circuits
The CT Clock and Frame Monitor circuits check the period of the C8_A_io and the C8_B_io clocks and the FRAME_A_io and FRAME_B_io frame pulses. According to the H.110 specification, the C8 period is 122 ns with a tolerance of +/-35 ns measured between rising edges. If C8 falls outside the range of [87 ns,157 ns], the clock is rejected and the fail signal (FAIL_A or FAIL_B) becomes high. The Frame pulse period is measured with respect to the C8 clock. The frame pulse period must have exactly 1024 C8 cycles. Otherwise, the fail signal (FAIL_A or FAIL_B) becomes high. When the CT BUS clock and frame pulse signals return to normal, the FAIL_A or FAIL_B signal returns to logic low.
16.5
Reference Monitor Circuits
There are two Reference Monitor Circuits: one for the primary reference (PRI_REF) and one for the secondary reference (SEC_REF). These two circuits monitor the selected input reference signals and detect failures by setting up the appropriate fail outputs (SLS and PLS bits in the DHKR register, seeTable 23 on page 50). These fail signals are used in the Autodetect mode as the LOS_PRI and LOS_SEC signals to indicate when the reference has failed. The method of generating a failure depends on the selected reference. When the selected reference frequency is 8.192 MHz ("A Clocks" or "B Clocks"), the fail signals are passed through from the CT Clock and Frame Monitor circuit outputs FAIL_A and FAIL_B, and used directly to set the SLS and PLS bits, accordingly. For all other reference frequencies (8 kHz, 1.544 MHz and 2.048 MHz), the following checks are performed: * * For all references, the "minimum 90 ns" check is done. This is required by the H.110 specifications - both low level and high level of the reference must last for minimum 90 ns each. The "period in the specified range" check is done for all references. The length of the period of the selected input reference is checked to verify if it is in the specified range. For the E1 (2.048 MHz clock) or the T1 (1.544 MHz clock) reference, the period of the clock can vary within the range of 1 +/- 1/4 of the defined clock period which is 488 ns for the E1 clock and 648 ns for T1 clock. For the 8 kHz reference, the variation is from 1 +/- 1/32 period. If the selected reference is E1 or T1, "64 periods in the specified range" check is done. The selected reference is observed for a long period (64 reference clock cycles) and checked to verify if it is within the specified range - from 62 to 66 clock periods.
*
These reference signal verifications include a complete loss or a large frequency shift of the selected reference signal. When the reference signal returns to normal, the LOS_PRI and LOS_SEC signals will return to logic low.
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16.6 State Machine Circuit
Data Sheet
The State Machine handles the reference selection. Depending on REF_SEL and LOS signals (selection between primary reference failure and PRI_LOS and between secondary reference failure and SEC_LOS), the state machine selects PRI_REF or SEC_REF as the current input reference and dictates the PLL Circuit mode: Normal or Holdover Mode. In the Normal Mode, the DPLL output clocks are locked to the selected input reference (PRI_REF or SEC_REF). In the Holdover Mode, the DPLL clocks retain the phase and frequency values they had 32 to 64 ms prior to moving from the Normal to the Holdover Mode. When going from the Holdover to the Normal Mode, the State Machine activates the MTIE circuit and goes through the states MTIE PRI or MTIE SEC to prevent a phase shift of the output clocks during the DPLL reference switch (from PRI_REF to SEC_REF and vice versa). The state diagram is given in Figure 7, "State Machine Diagram" on page 25.
RESET Pin = 0 and XX0 RESET Pin = 0 and XX1
Normal PRI
0
Normal SEC
4
0X0 or 011 1XX or X01 MTIE PRI 1X0 or X01 0X0 or 011 Holdover PRI 100 or X01 2 3
100 or X01 0X0 or X1X MTIE SEC 100 or X01 7
0X0 or X11
0X0 or 011
Holdover SEC
6
XXX = {LOS_PRI, LOS_SEC, REF_SEL}
Figure 7 - State Machine Diagram
16.7
Modes of Operation
The DPLL can operate in two main modes: Normal and Holdover Mode. Each of these modes has two states: primary or secondary state. The state depends on which reference is currently selected as the preferred reference PRI_REF or SEC_REF.
16.7.1
Normal Mode
Normal Mode is typically used when a clock source synchronized to the network is required. In the Normal Mode, the DPLL provides timing (C32/64, CT_C8, C2M and C1M5o) and frame synchronization (CT_FRAME) signals which are synchronized to one of two input references (PRI_REF or SEC_REF). The input reference signal may have a nominal frequency of 8 kHz, 1.544 MHz, 2.048 MHz or 8.192 MHz. From a device reset condition or after reference switch, the DPLL can take up to 50 seconds to phase lock the output signals to the selected input reference signal.
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16.7.2 Holdover Mode
Data Sheet
Holdover Mode is typically used for short durations while network synchronization is temporarily disrupted. If the FDM1-0 bits are programmed to `01' in the DOM2 register and the PRI_LOS and SEC_LOS pins are high, the DPLL is in the Holdover Mode. The DPLL can also be in the Holdover Mode if the FDM1-0 bits are programmed to `00' and the SLS and PLS bit are observed as `11' in the DPLL House Keeping Register (DHKR). In the Holdover Mode, the DPLL provides timing and synchronization signals which are based on storage techniques and are not locked to an external reference signal. The storage value is determined while the device is in Normal Mode and locked to an external reference signal. When the DPLL is in the Normal Mode and locks to the input reference signal, a numerical value corresponding to the DPLL output reference frequency is stored alternately in two memory locations every 32 ms. When the device is switched into the Holdover Mode, the value in memory from between 32 ms and 64 ms ago is used to set the output frequency of the device. The frequency stability of the Holdover Mode is 0.07 ppm, which translates to a worst case 49 frame (125 s) slips in 24 hours. Two factors affect the frequency stability of the Holdover Mode. The first factor is the drift on the frequency of the master clock (C20i) while in the Holdover Mode. Drift on the master clock directly affects the Holdover Mode stability. Note that the absolute master clock stability does not affect the Holdover Frequency stability, only the change in C20i stability while in Holdover. For example, a 32 ppm master clock may have a temperature coefficient of 0.1 ppm/ C. So a 10 degree change in temperature, while the DPLL is in the Holdover Mode may result in an additional offset (over the 0.07 ppm) in frequency stability of 1 ppm, which is much greater than the 0.07 ppm of the DPLL. The second factor affecting Holdover frequency stability is large jitter on the reference input prior to the mode switch.
16.7.3
Freerun Mode
When the DPLL is in the Holdover Mode and the HRST bit of the DOM2 register is pulsed logic high (or held high continuously), the device is in Freerun Mode. In Freerun Mode, the DPLL provides timing and synchronization signals which are based on the frequency of the master clock (C20i) only, and are not synchronized to the reference input signals. The frequency of the output signals is an ideal frequency with the freerun accuracy of -0.03 ppm plus the accuracy of the master clock (i.e., CT_C8 has frequency of 8.192 MHz +/- C20i_accuracy - 0.03 ppm). Freerun Mode is typically used when a master clock source is required, or immediately following system power-up before network synchronization is achieved.
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17.0 Phase Locked Loop (PLL) Circuit
Data Sheet
As shown in Figure 8, "Block Diagram of the PLL Module" on page 27, the PLL module consists of a Skew Control, Maximum Time Interval Error (MTIE), Phase Detector, Phase Offset Adder, Phase Slope Limiter, Loop Filter, Digitally Controlled Oscillator (DCO), Divider and Frequency Select MUX modules.
MTIE_RESET SKEW_CONTROL PHASE_OFFSET REF
HOLDOVER_RESET HOLDOVER C32/64
Skew Control (Fig 18)
REF_VIR
MTIE
MTIE_DONE MTIE_START
Phase Detector
Phase Offset Adder
Phase Slope Limiter
Loop Filter
CT_C8
DCO
Divider
C2M C1M5o CT_FRAME
FRAME FREQ_MOD
FEEDBACK
Frequency Select MUX
Figure 8 - Block Diagram of the PLL Module
17.1
Skew Control
The circuit delays a selected reference input with a tapped delay line with seven taps - see Figure 9, "Skew Control Circuit Diagram" on page 27. The maximum delay of the per unit delay element is factored at intervals of 3.5 ns. The tap is selected by the SKEW_CONTROL bus which is programmed by the SKC2-SKC0 bits of the DPLL Output Adjustment (DPOA) register. The skew of this input will result in a static phase offset which varies from 0 to 7 steps of the maximum delay per unit delay element, between the input and the outputs of the DPLL.
reference input
SKEW_CONTROL
Figure 9 - Skew Control Circuit Diagram
17.2
Maximum Time Interval Error (MTIE)
The MTIE circuit prevents any significant change in the output clock phase during a reference switch. Because the input references can have any relationship between their phases and the output follows the selected input reference, any switch from one reference to another could cause a large phase jump in the output clock if such a circuit did not exist. This large phase jump could cause significant data loss. The MTIE circuit keeps the phase difference between the output clock of the DPLL and the input reference the same as if the reference switch had not taken place.
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MUX
delayed reference
ZL50031
Data Sheet
During a reference switch, the State Machine module first changes the mode of the DPLL from the Normal to the Holdover Mode. In the Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates very accurate outputs using storage techniques. Because the input reference coming from the Skew Control circuit is asynchronous to the sampling clock used in the MTIE circuit, a phase error may exist between the selected input reference signal and the output signal of the DPLL. In the worst case, the Maximum Time Interval Error (MTIE) is one period of the internally used clock cycle (65.536 MHz if the selected reference frequency is 8 kHz, 2.048 MHz and 8.192 MHz, and 49.408 MHz when the selected reference frequency is 1.544 MHz). This phase error is a function of the difference in phase between the two input reference signals during reference rearrangements. Each time a reference switch is made, the delay between the input signal and the output signal can change. The value of this delay is the accumulation of the error measured during each reference switch. After many switches from one reference to another, the delay between the selected input reference and the DPLL output clocks can become unacceptably large. The user should provide MTIE reset (set MRST bit in the DOM2 register to high) causing output clocks to align to the nearest edge of the selected input reference. It is recommended that the MTIE is reset after multiple reference switchings and the device falls back to its initial reference. The MTIE MUST be kept in the reset mode when the ZL50031 is operating in the slave mode.
17.3
Phase Detector
The Phase Detector circuit compares the virtual reference signal from the MTIE Circuit with the feedback signal from the Frequency Select MUX circuit with respect to their rising edges, and provides an error signal corresponding to the phase difference between the two. This error signal is passed to the Phase Offset Adder Circuit. The Frequency Select MUX allows the proper feedback signal to be selected (e.g., 8 kHz, 1.544 MHz, 2.048 MHz or 8.192 MHz).
17.4
Phase Offset Adder
The Phase Offset Adder Circuit adds the PHASE_OFFSET word (bits POS6-POS0 of the DPLL Output Adjustment register - see Table 22 on page 50) to the error signal from the Phase Detector circuit to create the final phase error. This value is passed to the Phase Slope Limiter circuit. The PHASE_OFFSET word can be positive or negative. Since the PLL will stabilize to a situation where the average of the sum of the phase offset word and the phase detector output is zero, a nonzero value in the input of the Phase Offset Adder circuit will result in a static phase offset between the input and output signals of the DPLL. Together with the Skew Control bits (SKC2-0), users can program a static phase offset between -960 ns and +990 ns if the selected input reference of the DPLL is either 8 kHz or 2.048 MHz. If the selected reference is 1.544 MHz, the programmable phase offset is between -1.27 s and 1.30 s. For the programmable ranges mentioned above, the resolution is 1.9 ns per step. See Table 22 on page 50 for the content of the DPOA register. When the selected input reference frequency of the DPLL is 8.192 MHz ("A Clocks" or "B Clocks" are selected as the reference), the Phase Offset Adder is bypassed. The output of the Phase Detector circuit is connected directly to the input of the Phase Slope Limiter circuit. When an 8.192 MHz clock (C8_A_io or C8_B_io) is used as the reference in the Secondary Master or the Slave mode, the H.110 standard requires the output clock to always follow the input reference on an edge-to-edge basis, so the static phase offset is not required.
17.5
Phase Slope Limiter
The limiter receives the error signal from the Phase Offset Adder circuit and ensures that the DPLL responds to all input transient conditions with a maximum output phase slope of 7.6 ns per 125 s. Because of this slope, the ZL50031 is within the maximum phase slope of 81 ns per 1.326 ms specified by the Telcordia GR-1244-CORE standard. The frequency stability of the Holdover Mode is 0.07 ppm, which translates to a worst case 49 frame (125 s) slips in 24 hours. This is better than the Telcordia GR-1244-CORE Stratum 3 requirement of 0.37 ppm (255 frame slips per 24 hours).
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17.6 Loop Filter
Data Sheet
The Loop Filter circuit gives frequency offset to the DCO circuit, based on the phase difference between the input and the feedback reference. It is similar to a first order low pass filter, with two positions for cut-off frequency (-3 dB attenuation) depending on the selected reference frequency, and it largely determines the jitter transfer function of the DPLL. In Primary Master mode when the selected input reference frequency is 2.048 MHz, 1.544 MHz or 8 kHz, the cutoff frequency is approximately at 1.52 Hz and all the reference variations, including jitter, are attenuated according to the DPLL jitter transfer function (see Figure 10, "DPLL Jitter Transfer Function Diagram - Wide Range of Frequencies" on page 31 and Figure 11, "Detailed DPLL Jitter Transfer Function Diagram" on page 32). The Loop Filter circuit ensures that the jitter transfer requirements in ETS 300-011 and Telecordia GR-499-CORE are met when the selected reference frequency is 2.048 MHz, 1.544 MHz or 8 kHz. When the selected input reference frequency is 8.192 MHz (i.e., in Secondary Master or Slave modes), the reference variations are bypassed to the output clocks. The cut-off frequency is at about 100 kHz, well beyond 500 Hz, the corner frequency of the Telcordia GR-1244-CORE input jitter tolerance curve. The storage techniques, which enable generating very accurate output frequencies during the Holdover Mode of DPLL, are built into the Loop Filter circuit. When no jitter is presented on the selected input reference, the holdover frequency stability is 0.007 ppm.
17.7
Digitally Controlled Oscillator (DCO)
The DCO circuit adds frequency offset from the Loop Filter (which represents the phase error between the input and the feedback reference), to the ideal center frequency value and generates an appropriately corrected output high speed clock. In the Normal Mode, the DCO circuit provides an output signal which is frequency and phase locked to the selected input reference signal. In the Holdover Mode, the DCO circuit is running at a frequency that is equal to the frequency which was generated by the DCO circuit when the DPLL was in the Normal Mode. In the Freerun Mode, the DCO circuit is freerunning at its center frequency with an output accuracy equal to the accuracy of the device master clock (C20i).
17.8
Divider
The Divider Circuit divides the DCO output frequency down to the required outputs. The following outputs are generated: * * C64 (65.536 MHz clock) - used as the internal clock for the ZL50031 device. CT_C8 (8.192 MHz clock), C2M (2.048 MHz clock), C1M5o (1.544 MHz clock) and CT_FRAME (8 kHz negative frame pulse) - feedback reference signals to the Frequency Select MUX Circuit.
The CT_FRAME and the CT_C8 are required clocks. C1M5o is provided as an output clock of the ZL50031. The duty cycle of all output signals is independent of the duty cycle of the device master clock, C20i. The CT_C8, C2M and C1M5o clocks have nominal 50% duty cycle, The output frame pulse (CT_FRAME) is generated in such a way that it is always aligned with the CT_C8 clock to form the required H.110 CT Bus clock and frame pulse shape (when the CT_FRAME is low the rising edge of the CT_C8 defines the frame boundary). Depending on the selected input reference frequency, the CT_FRAME is generated in the following way: * When the input reference frequency is 8 kHz, the output frame pulse is aligned with the rising edge of the reference.
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* *
Data Sheet
When the reference frequency is either 2.048 MHz or 1.544 MHz, the CT_FRAME randomly defines the output frame boundary, always keeping the described relation to the CT_C8 clock. When the reference frequency is 8.192 MHz, the output frame pulse (CT_FRAME) has to be aligned with the input frame pulse (FRAME_A_io or FRAME_B_io). Since an 8.192 MHz clock (either C8_A_io or C8_B_io) is used as the reference clock, the selected frame pulse from the Frame Select MUX is provided as the input to the Divider circuit and the CT_FRAME is synchronized to it.
17.9
Frequency Select MUX Circuit
According to the selected input reference of the DPLL, this MUX will select the appropriate output frequency to be the feedback signal to the PLL and MTIE Circuits.
18.0
Measures of Performance
The following are some the DPLL performance indicators and their corresponding definitions.
18.1
Intrinsic Output Jitter
Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may also be measured when the device is in a non-synchronizing mode, such as freerun or holdover, by measuring the output jitter of the device. Intrinsic jitter is usually measured with various band-limiting filters depending on the applicable standards. See "AC Electrical Characteristics- Output Clock Jitter Generation (Unfiltered)" on page 64 for jitter values.
18.2
Jitter Tolerance
Jitter tolerance is a measure of the ability of a PLL to operate properly without cycle slips (i.e., remain in lock and regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied jitter magnitude and the jitter frequency depend on the applicable standards. The input jitter tolerance of the DPLL depends on the selected reference frequency and can not exceed: 15 U.I. for E1 or T1 references, and 1 U.I. for 8 kHz references.
18.3
Jitter Transfer
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. In slave and secondary master mode the H.110 standard requires the "B Clocks" to be edge-synchronous with the "A Clocks", as long as jitter on the "A Clocks" meets Telcordia GR-1244-CORE specifications. Therefore in these two modes no jitter attenuation is performed. In primary master mode the jitter attenuation of the DPLL is determined by the internal 1.52 Hz low pass Loop Filter and the Phase Slope Limiter. Figure 10, "DPLL Jitter Transfer Function Diagram - Wide Range of Frequencies" on page 31 shows the DPLL jitter transfer function diagram in a wide range of frequencies, while Figure 11, "Detailed DPLL Jitter Transfer Function Diagram" on page 32 is the portion of the diagram from Figure 10 around 0 dB of the jitter transfer amplitude. At this point it is possible to see that when operating in primary master mode the DPLL is a second order, type 2 PLL. The jitter transfer function can be described as a low pass filter to 1.52 Hz 20 dB/decade, with peaking less then 0.5 dB.
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Data Sheet
All outputs are derived from the same signal, therefore these diagrams apply to all outputs. Since 1 U.I. at 1.544 MHz (648 nsPP) is not equal to 1 U.I. at 2.048 MHz (488 nsPP). a transfer value using different input and output frequencies must be calculated in common units (e.g., seconds) as shown in the following example: What is the T1 and E1 output jitter when the T1 input jitter is 20 U.I. (T1 U.I. Units) and the T1 to T1 jitter attenuation is 18 dB, for a given jittering frequency? - A ----- 20 OutputT1 = InputT1 x10 - 18 ------- 20 OutputT1 = 20 x10 = 2.5UI ( T1 ) ( 1UIT1 ) OutputE1 = OutputT1 x --------------------( 1UIE1 ) ( 644ns ) OutputE1 = OutputT1 x ------------------- = 3.3UI ( T1 ) ( 488ns ) Using the method mentioned above, the jitter attenuation can be calculated for all combinations of inputs and outputs. Because intrinsic jitter is always present, the jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance).
Figure 10 - DPLL Jitter Transfer Function Diagram - Wide Range of Frequencies
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Data Sheet
Figure 11 - Detailed DPLL Jitter Transfer Function Diagram
18.4
Frequency Accuracy
Frequency accuracy is defined as the absolute tolerance of an output clock signal when the DPLL is not locked to an external reference, but is operating in the Freerun Mode. Because the output of the DCO Circuit has only discrete values, the output frequency of the DPLL has the limited accuracy of 0.03 ppm based upon the design implementation. In addition, the master clock (C20i) accuracy also directly affects the freerun accuracy. The freerun accuracy is then, 0.03 ppm plus the master clock accuracy.
18.5
Holdover Frequency Stability
Holdover frequency stability is defined as the maximum fractional frequency offset of an output clock signal when it is operating using a stored frequency value. For the DPLL, the stored value is determined while the device is in Normal Mode and locked to an external reference signal. As a result, when the DPLL is in the Normal Mode, the stability of the master clock (C20i) does not affect the holdover frequency stability because the DPLL will compensate for master clock changes while in Normal Mode. However, when the DPLL is in the Holdover Mode, the stability of the master clock does affect the Holdover frequency stability. The holdover frequency stability is 0.07 ppm assuming that the C20i frequency is held constant.
18.6
Locking Range
The locking range is the input frequency range over which the DPLL must be able to pull into synchronization and to maintain the synchronization. The locking range is defined by the Loop Filter Circuit and is equal to +/- 298 ppm. Note that the locking range is related to the master clock (C20i). If the master clock is shifted by -100 ppm, the whole locking range also shifts -100 ppm downwards to be: -398 ppm to 198 ppm.
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18.7 Phase Slope
Data Sheet
The phase slope or the phase alignment speed is the rate at which a given signal changes phase with respect to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal. Many telecom standards like Telcordia GR-1244CORE state that the phase slope may not exceed a certain value, usually 81 ns/1.327 ms (61 ppm). This can be achieved by limiting the phase detector output to 61 ppm or less. When operating in primary master mode, the Phase Slope Limiter Circuit achieves the maximum phase slope of 56 ppm or 7.0 ns/125 s. When operating in secondary master or slave mode, the output edges follow the input edges in accordance with the H.110 standard.
18.8
Maximum Time Interval Error (MTIE)
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period. For the DPLL, the maximum time interval error is less than 21 ns per reference switch.
18.9
Phase Lock Time
The Phase Lock Time is the time it takes the PLL to phase lock to the input signal. Phase lock occurs when the input and the output signals are not changing in phase with respect to each other (not including jitter). Lock time is very difficult to determine because it is affected by many factors which include: * * * * initial input to output phase difference initial input to output frequency difference PLL loop filter PLL limiter
Although a short phase lock time is desirable, it is not always possible to achieve due to other PLL requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time, but better (smaller) phase slope performance (limiter) results in longer lock times. The DPLL loop filter and limiter were optimized to meet the Telcordia GR-499-CORE jitter transfer and Telcordia GR-1244-CORE phase alignment speed requirements. Consequently, phase lock time, which is not a standards requirement, is less than 50 seconds.
19.0
Initialization of the ZL50031
During power up, the TRST pin should be pulled low to ensure that the ZL50031 is in the functional mode. An external pull-down resistor is required on this pin so that the ZL50031 will not enter the JTAG test mode during power up. After power up, the contents of the connection memory can be in any state. The ODE pin should be held low after power up to keep all serial outputs in a high impedance state until the microprocessor has initialized the switching matrix. This procedure prevents two serial outputs from driving the same stream simultaneously. During the microprocessor initialization routine, the microprocessor should program the desired active paths through the switch. The memory block programming feature can also be used to quickly initialize the backplane and local connection memories. When this process is completed, the microprocessor controlling the ZL50031 can bring the ODE pin high to relinquish the high impedance state control.
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20.0 JTAG Support
Data Sheet
The ZL50031 JTAG interface conforms to the Boundary-Scan IEEE1149.1 standard. The operation of the boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller.
20.1
Test Access Port (TAP)
The Test Access Port (TAP) accesses the ZL50031 test functions. It consists of three input pins and one output pin as follows: * Test Clock Input (TCK) - TCK provides the clock for the test logic. The TCK does not interfere with any onchip clock and thus remains independent in the functional mode. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. Test Mode Select Input (TMS) - The TAP Controller uses the logic signals received at the TMS input to control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to Vdd when it is not driven from an external source. Test Data Input (TDi) - Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to Vdd when it is not driven from an external source. Test Data Output (TDo) - Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or data register are serially shifted out towards the TDo. The data out of the TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is set to a high impedance state. Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to Vdd when it is not driven from an external source. An external pull-down resistor is required on this pin so that the ZL50031 will not enter the JTAG test mode during power up.
*
*
*
*
20.2
Instruction Register
The ZL50031 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG Interface contains a fourbit instruction register. Instructions are serially loaded into the instruction register from TDi when the TAP Controller is in its shifted-IR state. These instructions are subsequently decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current and to define the serial test data register path that is used to shift data between TDi and TDo during data register scanning.
20.3
Test Data Register
As specified in IEEE 1149.1, the ZL50031 JTAG interface contains three test data registers: * * * The Boundary-Scan Register - The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the ZL50031 core logic. The Bypass Register - The Bypass register is a single stage shift register that provides a one-bit path from TDi to TDo. The Device Identification Register - The JTAG device ID for the ZL50031 is 0086614BH. Version<31:28>:0000 Part No. <27:12>:0000 1000 0110 0110 Manufacturer ID<11:1>: 0001 0100 101 LSB<0>:1
20.4
BSDL
A BSDL (Boundary Scan Description Language) file is available from Zarlink Semiconductor to aid in the use of the IEEE 1149.1 test interface.
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21.0 Register Descriptions
Data Sheet
Read/Write Address: 0000H
Reset Value: 0000H
15 0 14 0 13 STS3 12 STS2 11 STS1 10 STS0 9 PRST 8 CBEBB 7 SBERB 6 CBERL 5 SBERL 4 0 3 MBP 2 MS2 1 MS1 0 MS0
Bit 15-14 13-12
Name Unused STS3-2 Reserved.
Description
ST-BUS Frame Pulse and Clock Output Selection 1: These two bits are used to select different frequencies for the ST-BUS output frame pulse (ST_FPo1) and clock (ST_CKo1).
STS3 STS2 ST_FPo1 Pulse Width 0 0 244 ns 0 1 122 ns 1 0 61 ns ST_CKo1 Frequency 4.096 MHz 8.192 MHz 16.384 MHz
11-10
STS1-0
ST-BUS Frame Pulse and Clock Output Selection 0: These two bits are used to select different frequencies for the ST-BUS output frame pulse (ST_FPo0) and clock (ST_CKo0).
STS1 STS0 ST_FPo0 Pulse Width 0 0 244 ns 0 1 122 ns 1 0 61 ns ST_CKo0 Frequency 4.096 MHz 8.192 MHz 16.384 MHz
9 8 7
PRST CBERB SBERB
PRBS Reset: When high, the PRBS transmitter output will be initialized. Backplane Bit Error Rate Test Clear: A low to high transition of this bit will reset the backplane internal bit error counter and the Backplane BER register (BBERR). Backplane Start Bit Error Rate Test: A low to high transition in this bit starts the backplane bit error rate test. The bit error test result is kept in the Backplane BER register (BBERR). Local Bit Error Rate Test Clear: A low to high transition of this bit will reset the local internal bit error counter and the Local BER register (LBERR). Local Start Bit Error Rate Test: A low to high transition in this bit starts the local bit error rate test. The bit error test result is kept in the Local BER register (LBERR). Reserved. In normal functional mode, this bit MUST be set to zero. Memory Block Programming: When this bit is high, the connection memory block programming feature is ready for the programming of bit 13 to bit 15 of the backplane connection memory and local connection memory. When it is low this feature is disabled. Table 8 - Control Register (CR) Bits
6 5 4 3
CBERL SBERL Unused MBP
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Bit 2-0 Name MS2-0 Description
Data Sheet
Memory Select Bits: These three bits are used to select different connection and data memories.
MS2 0 0 0 0 1 MS1 0 0 1 1 0 MS0 0 1 0 1 0 Memory Selection Local Connection Memory Read/Write Reserved Backplane Connection Memory Read/Write Local Data Memory Read Backplane Data Memory Read
Table 8 - Control Register (CR) Bits (continued)
Read/Write Address: 0001H
Reset Value: 0000H
15 0 14 BMS 13 0 12 0 11 0 10 LG31 9 LG30 8 0 7 LG21 6 LG20 5 0 4 LG11 3 LG10 2 0 1 LG01 0 LG00
Bit 15 14
Name Unused BMS
Description Reserved. In normal functional mode, this bit MUST be set to zero. Backplane Mode Select: This bit refers to the different modes for the backplane interface.
BMS 0 1 Switching Mode Usable Streams 8 Mbps BSTio0 - 31 16 Mbps BSTio0 - 15
13-11 10-9
Unused LG31-30
Reserved. In normal functional mode, these bits MUST be set to zero. Local Group 3 Mode Select: These two bits refer to different switching modes for group 3 (LSTi12-15 and LSTo12-15) of the local interface.
LG31 0 0 1 1 LG30 0 1 0 1 Switching Mode 8 Mbps 4 Mbps 2 Mbps Reserved
8
Unused
Reserved. In normal functional mode, this bit MUST be set to zero. Table 9 - Device Mode Selection (DMS) Register Bits
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Bit 7-6 Name LG21-20 Description
Data Sheet
Local Group 2 Mode Select: These two bits refer to different switching modes for group 2 (LSTi8-11 and LSTo8-11) of the local interface.
LG21 0 0 1 1 LG20 0 1 0 1 Switching Mode 8 Mbps 4 Mbps 2 Mbps Reserved
5 4-3
Unused LG11-10
Reserved. In normal functional mode, this bit MUST be set to zero. Local Group 1 Mode Select: These two bits refer to different switching modes for group 1 (LSTi4-7 and LSTo4-7) of the local interface.
LG11 0 0 1 1 LG10 0 1 0 1 Switching Mode 8 Mbps 4 Mbps 2 Mbps Reserved
2 1-0
Unused LG01-00
Reserved. In normal functional mode, this bit MUST be set to zero. Local Group 0 Mode Select: These two bits refer to different switching modes for group 0 (LSTi0-3 and LSTo0-3) of the local interface.
LG01 0 0 1 1 LG00 0 1 0 1 Switching Mode 8 Mbps 4 Mbps 2 Mbps Reserved
Table 9 - Device Mode Selection (DMS) Register Bits (continued)
Read/Write Address: 0002H Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 BBPD2 7 BBPD1 6 BBPD0 5 LBPD2 4 LBPD1 3 LBPD0 2 BPE 1 0 0 0
Bit 15-9
Name Unused
Description Reserved. In normal functional mode, these bits MUST be set to zero. Table 10 - Block Programming Mode (BPM) Register Bits
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Bit 8-6 Name BBPD2-0 Description
Data Sheet
Backplane Block Programming Data Bits: These bits carry the value to be loaded into the backplane connection memory block whenever the Memory Block Programming feature is activated. After the MBP bit in the Control Register is set to high and the BPE is set to high, the contents of the bits BBPD2 - 0 are loaded into bits 15 - 13 of the backplane connection memory. Bits 12 - 0 of the backplane connection memory are programmed to be zero. Local Block Programming Data Bits: These bits carry the value to be loaded into the local connection memory whenever the Memory Block Programming feature is activated. After the MBP bit in the Control Register is set to high and the BPE is set to high, the contents of the bits LBPD2 - 0 are loaded into bits 15 - 13 of the local connection memory. Bits 12 - 0 of the local connection memory are programmed to be zero. Block Programming Enable: A low to high transition of this bit enables the Memory Block Programming function. The BPE, BBPD2-0 and LBPD2-0 in the BPM register must be defined in the same write operation. Once the BPE bit is set to high, ZL50031 requires two frames to complete the block programming. After the block programming has finished, the BPE bit returns to low to indicate that the operation is complete. When BPE is high, BPE or MBP can be set to low to abort the programming operation. When BPE is high, the other bits in the BPM register must not be changed for two frames to ensure proper operation. Whenever the microprocessor writes BPE to be high to start the block programming function, the user must maintain the same logical value on the other bits in the BPM register to avoid any change in the setting of the device.
5-3
LBPD2-0
2
BPE
1-0
Unused
Reserved. In normal functional mode, these bits MUST be set to zero. Table 10 - Block Programming Mode (BPM) Register Bits (continued)
Read/Write Addresses:
0004H for LIDR0 register, 0006H for LIDR2 register, 0008H for LIDR4 register,
0005H for LIDR1 register, 0007H for LIDR3 register, 0009H for LIDR5 register,
Reset Value: 0000H
15 LIDR0 0 14 LID24 13 LID23 12 LID22 11 LID21 10 LID20 9 LID14 8 LID13 7 LID12 6 LID11 5 LID10 4 LID04 3 LID03 2 LID02 1 LID01 0 LID00
LIDR1 0
LID54
LID53
LID52
LID51
LID50
LID44
LID43
LID42
LID41
LID40
LID34
LID33
LID32
LID31
LID30
LIDR2 0
LID84
LID83
LID82
LID81
LID80
LID74
LID73
LID72
LID71
LID70
LID64
LID63
LID62
LID61
LID60
LIDR3 0
LID114
LID113
LID112
LID111
LID110
LID104
LID103
LID102
LID101
LID100
LID94
LID93
LID92
LID91
LID90
LIDR4 0
LID144
LID143
LID142
LID141
LID140
LID134
LID133
LID132
LID131
LID130
LID124
LID123
LID122
LID121
LID120
LIDR5 0
0
0
0
0
0
0
0
0
0
0
LID154
LID153
LID152
LID151
LID150
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Name LIDn4-0 (See Note 1) Description
Data Sheet
Local Input Delay Bits 4 - 0: These five bits define how long the serial interface receiver takes to recognize and to store bit 0 from the LSTin input pins: i.e., to start a new frame. The input delay can be selected to +7 3/4 data rate clock periods from the frame boundary.
Note 1: n denotes an LSTi stream number from 0 to 15.
Table 11 - Local Input Bit Delay Registers (LIDR0 to LIDR5) Bits
Corresponding Delay Bits Local Input Bit Delay LIDn4 No clock period shift (Default) + 1/4 data rate clock period + 1/2 data rate clock period + 3/4 data rate clock period + 1 data rate clock period + 1 1/4 data rate clock period + 1 1/2 data rate clock period + 1 3/4 data rate clock period + 2 data rate clock period .......... + 7 3/4 data rate clock period 1 1 0 0 0 0 0 0 0 0 0 LIDn3 0 0 0 0 0 0 0 0 1 LIDn2 0 0 0 0 1 1 1 1 0 ........... 1 1 1 LIDn1 0 0 1 1 0 0 1 1 0 LIDn0 0 1 0 1 0 1 0 1 0
Table 12 - Local Input Bit Delay Programming
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ST_FPo0/1
Data Sheet
input data
bit7
Bit Delay 0 LID=00000 Bit Delay 1/4 LID=00001 Bit Delay 1/2 LID=00010 Bit Delay 3/4 LID=00011 Bit Delay 1 LID=00100 Bit Delay 1 1/2 LID=00101
input data
bit7
input data
bit7
input data
bit7
input data
bit7
input data
bit7
Figure 12 - Local Input Bit Delay Timing
Note: The data is sampled at the 3/4 bit point.
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Read/Write Addresses: Reset value:
15 BOAR0 BOA 71 14 BOA 70 13 BOA 61
Data Sheet
001CH for BOAR0 register, 001EH for BOAR2 register, 0000H for all BOAR registers.
12 BOA 60 11 BOA 51 10 BOA 50 9 BOA 41 8 BOA 40 7
001DH for BOAR1 register, 001FH for BOAR3 register,
6 BOA 30 5 BOA 21 4 BOA 20 3 BOA 11 2 BOA 10 1 BOA 01 0 BOA 00
BOA 31
BOAR1
BOA 151
BOA 150
BOA 141
BOA 140
BOA 131
BOA 130
BOA 121
BOA 120
BOA 111
BOA 110
BOA 101
BOA 100
BOA 91
BOA 90
BOA 81
BOA 80
BOAR2
BOA 231
BOA 230
BOA 221
BOA 220
BOA 211
BOA 210
BOA 201
BOA 200
BOA 191
BOA 190
BOA 181
BOA 180
BOA 171
BOA 170
BOA 161
BOA 160
BOAR3
BOA 311
BOA 310
BOA 301
BOA 300
BOA 291
BOA 290
BOA 281
BOA 280
BOA 271
BOA 270
BOA 261
BOA 260
BOA 251
BOA 250
BOA 241
BOA 240
Name) BOAn1-0 (See Note 1)
Description Backplane Output Advancement Bits 1 - 0: These two bits represent the amount of offset that a particular stream output can be advanced. When the offset is zero, the serial output stream has normal alignment with the frame pulse.
BOAn1 0 0 1 1 BOAn0 0 1 0 1 Output Advancement 0 ns 7.5 ns 15 ns 22.5 ns 8.192 Mbps (bit) 0 - 1/16 - 1/8 - 3/16 16.384 Mbps (bit) 0 - 1/8 - 1/4 - 3/8
Note 1: n denotes a BSTio stream number from 0 to 31.
Table 13 - Backplane Output Advancement Registers (BOAR0 to BOAR3) Bit
FRAME_A_io or FRAME_B_io C64 (internal clock) 8 Mbps Stream
Bit 7
advancement is 0 ns BOA=00 advancement is 7.5 ns BOA=01 advancement is 15 ns BOA=10 advancement is 22.5 ns BOA=11
8 Mbps Stream 8 Mbps Stream
Bit 7
Bit 7
8 Mbps Stream
Bit 7
denotes the starting point of the bit cell
Figure 13 - Example of Backplane Output Advancement Timing
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Zarlink Semiconductor Inc.
ZL50031
Read/Write Addresses: Reset value:
15 LOAR0 LOA 71 14 LOA 70 13 LOA 61 12 LOA 60 11 LOA 51
Data Sheet
0021H for LOAR1 register,
0020H for LOAR0 register, 0000H for all LOAR registers.
10 LOA 50 9 LOA 41 8 LOA 40 7 LOA 31 6 LOA 30 5 LOA 21
4 LOA 20
3 LOA 11
2 LOA 10
1 LOA 01
0 LOA 00
LOAR1
LOA1 LOA1 LOA1 LOA1 LOA1 LOA1 LOA1 LOA1 LOA1 LOA1 51 50 41 40 31 30 21 20 11 10
LOA 101
LOA1 LOA9 LOA9 LOA8 LOA8 00 1 0 1 0
Name LOAn1-0 (See Note 1)
Description Local Output Advancement Bits 1-0: These two bits represent the amount of offset that a particular stream output can be advanced. When the offset is zero, the serial output stream has normal alignment with the frame pulse.
LOAn1 0 0 1 1 LOAn0 0 1 0 1 Output Advancement 0 ns - 7.5 ns - 15 ns - 22.5 ns 2.048 Mbps (bit) 0 - 1/64 - 1/32 - 3/64 4.096 Mbps (bit) 0 - 1/32 - 1/16 - 3/32 8.192 Mbps (bit) 0 - 1/16 - 1/8 - 3/16
Note 1: n denotes a LSTo stream number from 0 to 15.
Table 14 - Local Output Advancement Registers (LOAR0 to LOAR1) Bits
ST_FPo0/1 C64 (internal clock) 8 Mbps Stream
Bit 7
advancement is 0 ns LOA=00 advancement is 7.5 ns LOA=01 advancement is 15 ns LOA=10 advancement is 22.5 ns LOA=11
8 Mbps Stream 8 Mbps Stream 8 Mbps Stream
Bit 7
Bit 7
Bit 7
denotes the starting point of the bit cell
Figure 14 - Local Output Advancement Timing
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Zarlink Semiconductor Inc.
ZL50031
Read/Write Address: 0027H Reset Value: 0000H 15 0 14 0 13 0 12 0 11 LBS A3 10 LBS A2 9 LBS A1 8 LBS A0 7 LBC A7 6 LBC A6 5 LBC A5 4 LBC A4 3 LBC A3 2 LBC A2
Data Sheet
1 LBC A1
0 LBC A0
Bit 15 - 12 11 - 8 7-0
Name Unused LBSA3 - 0 LBCA7 - 0
Description Reserved. In normal functional mode, these bits MUST be set to zero. Local BER Input Stream Address Bits: These bits refer to the local input data stream which receives the BER data. Local BER Input Channel Address Bits: These bits refer to the local input channel which receives the BER data.
Table 15 - Local Bit Error Rate Input Selection (LBIS) Register Bits
Read Address: 0028H Reset Value: 0000H
15 LBER 15 14 LBER 14 13 LBER 13 12 LBER 12 11 LBER 11 10 LBER 10 9 LBER 9 8 LBER 8 7 LBER 7 6 LBER 6 5 LBER 5 4 LBER 4 3 LBER 3 2 LBER 2 1 LBER 1 0 LBER 0
Bit 15 - 0
Name LBER15 - 0
Description Local Bit Error Rate Count Bits: These bits refer to the local bit error counts. This counter stops incrementing when it reaches the value 0xFFFF. Table 16 - Local Bit Error Rate Register (LBERR) Bits
Read/Write Address: 0029H Reset Value: 0000H
15 0 14 0 13 0 12 BBSA 4 11 BBSA 3 10 BBSA 2 9 BBSA 1 8 BBSA 0 7 BBCA 7 6 BBCA 6 5 BBCA 5 4 BBCA 4 3 BBCA 3 2 BBCA 2 1 BBCA 1 0 BBCA 0
Bit 15 - 13 12 - 8 7-0
Name Unused BBSA4 - 0 BBCA7 - 0
Description Reserved. In normal functional mode, these bits MUST be set to zero. Backplane BER Input Stream Address Bits: These bits refer to the backplane input data stream which receives the BER data. Backplane BER Input Channel Address Bits: These bits refer to the backplane input channel which receives the BER data.
Table 17 - Backplane Bit Error Rate Input Selection (BBIS) Register Bits
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Zarlink Semiconductor Inc.
ZL50031
Read Address: 002AH Reset Value: 0000H
15 BBER 15 14 BBER 14 13 BBER 13 12 BBER 12 11 BBER 11 10 BBER 10 9 BBER 9 8 BBER 8 7 BBER 7 6 BBER 6 5 BBER 5 4 BBER 4 3 BBER 3 2 BBER 2
Data Sheet
1 BBER 1
0 BBER 0
Bit 15 - 0
Name BBER15 -0
Description Backplane Bit Error Rate Count Bits: These bits refer to the backplane bit error count. This counter stops incrementing when it reaches the value 0xFFFF.
Table 18 - Backplane Bit Error Rate Register (BBERR) Bits
Read/Write Address: 002BH Reset Value: 0000H
15 CNEN 14 BEN 13 AEN 12 RPS 11 FS1 10 FS0 9 FP1 8 FP0 7 SS3 6 SS2 5 SS1 4 SS0 3 SP3 2 SP2 1 SP1 0 SP0
Bit 15 14
Name CNEN BEN
Description NREFo Output Enable Bit: When CNEN is low, NREFo output is disabled, i.e., tri-stated. When CNEN is high, NREFo output is enabled. B Clocks Output Enable Bit: When BEN is low, the "B Clocks" (C8_B_io and FRAME_B_io) are disabled, i.e., tri-stated - C8_B_io and FRAME_B_io behave as inputs. When BEN is high, the "B Clocks" are enabled - C8_B_io and FRAME_B_io behave as outputs.
13
AEN
A Clocks Output Enable Bit: When AEN is low, the "A Clocks" (C8_A_io and FRAME_A_io) are disabled, i.e., tri-stated - C8_A_io and FRAME_A_io behave as inputs. When AEN is high, the "A Clocks" are enabled - C8_A_io and FRAME_A_io behave as outputs.
12
RPS
Reference Selection Bit: When RPS is low, the preferred reference is the primary reference (PRI_REF). When RPS is high, the preferred reference is the secondary reference (SEC_REF). SEC_REF Frequency Selection Bits: These bits are used to select different clock frequencies for the secondary reference.
FS1 0 0 1 1 FS0 0 1 0 1 Secondary Reference 8 kHz 1.544 MHz 2.048 MHz 8.192 MHz ("A Clocks" or "B Clocks")
11 - 10
FS1- 0
Table 19 - DPLL Operation Mode (DOM1) Register Bits
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Zarlink Semiconductor Inc.
ZL50031
Read/Write Address: 002BH Reset Value: 0000H
15 CNEN 14 BEN 13 AEN 12 RPS 11 FS1 10 FS0 9 FP1 8 FP0 7 SS3 6 SS2 5 SS1 4 SS0 3 SP3 2 SP2
Data Sheet
1 SP1
0 SP0
Bit 9-8
Name FP1 - 0
Description PRI_REF Frequency Selection Bits: These bits are used to select different clock frequencies for the primary reference.
FS1 0 0 1 1 FS0 0 1 0 1 8 kHz 1.544 MHz 2.048 MHz 8.192 MHz ("A Clocks" or "B Clocks") Primary Reference
7-4
SS3 - 0
Secondary Clock Reference Input Selection Bits: These bits are used to select secondary reference input.
SS3 - SS0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Secondary Clock Reference Input CTREF1 CTREF2 "A Clocks" "B Clocks" Reserved Reserved Reserved Reserved LREF0 LREF1 LREF2 LREF3 Reserved Reserved Reserved Reserved
Table 19 - DPLL Operation Mode (DOM1) Register Bits (continued)
45
Zarlink Semiconductor Inc.
ZL50031
Read/Write Address: 002BH Reset Value: 0000H
15 CNEN 14 BEN 13 AEN 12 RPS 11 FS1 10 FS0 9 FP1 8 FP0 7 SS3 6 SS2 5 SS1 4 SS0 3 SP3 2 SP2
Data Sheet
1 SP1
0 SP0
Bit 3-0
Name SP3 - 0
Description Primary Clock Reference Input Selection Bits: These bits are used to select primary reference input.
SP3 - SS0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Primary Clock Reference Input CTREF1 CTREF2 "A Clocks" "B Clocks" Reserved Reserved Reserved Reserved LREF0 LREF1 LREF2 LREF3 Reserved Reserved Reserved Reserved
Table 19 - DPLL Operation Mode (DOM1) Register Bits (continued)
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Zarlink Semiconductor Inc.
ZL50031
Read/Write Address: 002CHr Reset Value: 0000H
15 0 14 0 13 0 12 0 11 HRST 10 MRST 9 FDM1 8 FDM0 7 BFEN 6 AFEN 5 CNIN 4 DIV1 3 DIV0 2 0 1
Data Sheet
0 CNS0
CNS1
Bit 15 - 12 11
Name Unused HRST
Description Reserved. In normal functional mode, these bits MUST be set to zero. DPLL Holdover Memory Reset Bit: When HRST is low, the DPLL holdover memory circuit is in functional mode. When HRST is high, the holdover memory circuit will be reset. While the DPLL is in Holdover Mode, pulsing HRST high (or holding it high continuously) will force the DPLL to the Freerun Mode. MTIE Reset Bit: When MRST is low, the DPLL MTIE circuit is in functional mode. When MRST is high, the MTIE circuit will be reset - the DPLL outputs will align with the nearest edge of the selected reference. When the ZL50031 is operating in the slave mode, this bit MUST be set high to keep the MTIE in the reset mode. Failure Detect Mode Bits: These two bits control how to choose the Failure Detection Mode.
FDM1 0 0 1 1 FDM0 0 1 0 1 Failure Detection Mode Autodetect - Automatic Failure Detection by internal reference monitor circuit External - Failure Detection controlled by external inputs (PRI_LOS and SEC_LOS) Forced Primary - The DPLL is forced to use primary reference Forced Secondary - The DPLL is forced to use secondary reference
10
MRST
9-8
FDM1 -0
7 6 5
BFEN AFEN CNIN
B Clocks Fail Output Enable Bit: When BFEN is low, FAIL_B output is disabled, i.e., tri-stated. When BFEN is high, FAIL_B output is enabled. A Clocks Fail Output Enable Bit: When AFEN is low, FAIL_A output is disabled, i.e., tri-stated. When AFEN is high, FAIL_A output is enabled. CTREF1 and CTREF2 Inputs Inverted: When CNIN is high, the CTREF1 and CTREF2 inputs will be inverted, prior to entering the DPLL module. When CNIN is low, the CTREF1 and CTREF2 inputs will not be inverted. Table 20 - DPLL Operation Mode (DOM2) Register Bits
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Zarlink Semiconductor Inc.
ZL50031
Bit 4 -3 Name DIV1 - 0 Description
Data Sheet
Divider Bits: These two bits define the relationship between the input reference and the NREFo output.
DIV1 0 0 1 1 DIV0 0 1 0 1 Input reference Input reference/193 (8 kHz signal when input reference clock = 1.544 MHz) Input reference/256 (8 kHz signal when input reference clock = 2.048 MHz) Reserved NREFo Output
2 1- 0
Reserved CNS1 - 0
Reserved. In normal functional mode, this bit MUST be set to zero. NREFo Source Selection Bits: These three bits select three of the LREF3 LREF0 to be the NREFo source.
CNS1 0 0 1 1 CNS0 0 1 0 1 NREFo Source LREF0 LREF1 LREF2 LREF3
Table 20 - DPLL Operation Mode (DOM2) Register Bits (continued)
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Zarlink Semiconductor Inc.
ZL50031
Bit
BEN (bit 14) AEN (bit 13) RPS (bit 12) FS1-0 (bits 11-10) Frequency of the secondary reference FP1-0 (bits 9-8) Frequency of the primary reference SS3-0 (bits 7-4) Secondary reference selection:
Data Sheet
Primary Master Mode
0 - Monitor "B Clocks" 1 - Drive "A Clocks" 0 - Preferred reference is PRI_REF 00 - 8 kHz 01 - 1.544 MHz 10 - 2.048 MHz
Secondary Master Mode
1 - Drive "B Clocks" 0 - Monitor "A Clocks" 0 - Preferred reference is PRI_REF 00 - 8 kHz 01 - 1.544 MHz 10 - 2.048 MHz
Slave Mode
0 - Monitor "B Clocks" 0 - Monitor "A Clocks" 0 - Preferred reference is PRI_REF 11 - 8.192 MHz Clock ("B Clocks")
00 - 8 kHz 01 - 1.544 MHz 10 - 2.048 MHz
11 - 8.192 MHz Clock
("A Clocks")
11 - 8.192 MHz Clock ("A Clocks")
DOM1 Register Bits
0000 - CTREF1 0001 - CTREF2 1000 - LREF0 1001 - LREF1 1010 - LREF2 1011 - LREF3
0000 - CTREF1 0001 - CTREF2 1000 - LREF0 1001 - LREF1 1010 - LREF2 1011 - LREF3
XXXX - C8_B_io When bits FS1-0 are set to 11, C8_B_io is always used as the secondary reference, regardless of the values of bits SS3-0. Output frame pulses are aligned to FRAME_B_io if secondary reference is the active reference XXXX - C8_A_io When bits FP1-0 are set to 11, C8_A_io is always used as the primary reference, regardless of the values of bits SP3-0. Output frame pulses are aligned to FRAME_A_io if primary reference is the active reference 1 - MTIE MUST be kept in the reset state in Slave mode 00 - Autodetect Mode 01 - External Mode (Note 1)
SP3-0 (bits 3-0) Primary reference selection:
0000 - CTREF1 0001 - CTREF2 1000 - LREF0 1001 - LREF1 1010 - LREF2 1011 - LREF3
XXXX - C8_A_io When bits FP1-0 are set to 11, C8_A_io is always used as the primary reference, regardless of the values of bits SP3-0. Output frame pulses are aligned to FRAME_A_io if primary reference is the active reference 0 - MTIE functional 1 - MTIE reset 00 - Autodetect Mode 01 - External Mode (Note 1)
MRST (bit 10) DOM 2 Register Bits FDM1, FDM0 (bits 9-8) Failure detect mode selection
0 - MTIE functional 1 - MTIE reset 00 - Autodetect Mode
* Note 1: It is assumed that the switching among references is done by external software control, if the External Mode is selected.
Table 21 - ZL50031 Mode Selection - By Programming DOM1 and DOM2 Registers
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Zarlink Semiconductor Inc.
ZL50031
Read/Write Address: 002DH Reset Value: 0000H
15 POS 6 14 POS 5 13 POS 4 12 POS 3 11 POS 2 10 POS 1 9 POS 0 8 0 7 0 6 0 5 0 4 0 3 0 2 SKC2
Data Sheet
1 SKC1
0 SKC0
Bit 15 - 9
Name POS6 - 0
Description Phase Offset Bits: These seven bits refer to the 2's complement phase word to control the DPLL output phase offset. The offset varies in steps of 15 ns if the reference is 8 kHz or 2.048 MHz. The offset varies in steps of 20 ns if the reference is 1.544 MHz. Reserved. In normal functional mode, these bits MUST be set to zero. Skew Control Bits: These three bits control the delay of the DPLL outputs from 0 to 7 steps in delay intervals of 3.5 ns. Table 22 - DPLL Output Adjustment (DPOA) Register Bits
8-3 2-0
Unused SKC2 - 0
Read/Write Address: 002EH for DHKR Register Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 SLS 5 PLS 4 CKM 3 Limit 2 State2 1 State1 0 State0
Bit 15 - 7 6 5 4
Name Unused SLS PLS CKM
Description Reserved. In normal functional mode, these bits MUST be set to zero. Secondary Loss Detection Bit (Read-only bit): When the secondary reference fails, this bit is set to high. Primary Loss Detection Bit (Read-only bit): When the primary reference fails, this bit is set to high. DPLL Output Clock Bit: When high, the primary output C32/64o is 65.536 MHz clock. When low, the primary output C32/64o is 32.768 MHz clock. This is the only writable bit in this register. Limit (Read-only bit): Indicates that DPLL Phase Slope Limiter limits input phase. State: These 3 bits indicate the state of the DPLL State Machine. Please refer to Figure 7, "State Machine Diagram" on page 25.
State 2-0 000 001 010 011 100 101 110 111 State Name NORMAL_PRI Reserved HOLDOVER_PRI MTIE_PRI NORMAL_SEC Reserved HOLDOVER_SEC MTIE_SEC
3 2-0
Limit State 2-0
Table 23 - DPLL House Keeping (DHKR) Register Bits
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Zarlink Semiconductor Inc.
ZL50031
15 BTM 2 14 BTM 1 13 BTM 0 12 BSAB 4 11 BSAB 3 10 BSAB 2 9 BSAB 1 8 BSAB 0 7 BCA B7 6 BCA B6 5 BCA B5 4 BCA B4 3 BCA B3 2 BCA B2
Data Sheet
1 BCA B1
0 BCA B0
Bit 15 -13
Name BTM2 - 0
Description Throughput Delay and Message Control Bits: These three bits control the backplane CT-Bus input or output.
BTM 2-0 000 Throughput Delay and Message Mode Control Per-channel variable delay from local interface; the content of the connection memory is the local data memory address of the switched input channel and stream. The backplane ST-BUS output is from local ST-BUS input. Per-channel constant delay from local interface; the content of the connection memory is the local data memory address of the switched input channel and stream. The backplane ST-BUS output is from local ST-BUS input. Per-channel variable delay from backplane interface; the content of the connection memory is the backplane data memory address of the switched input channel and stream. The backplane ST-BUS output is from the backplane CT-Bus input. Per-channel constant delay from the backplane interface; the content of the connection memory is the backplane data memory address of the switched input channel and stream. The backplaneST-BUS output is from backplane CT-Bus input. Per-channel message mode; only the lower byte (bits 7 to 0) of the connection memory location will be presented to the backplaneST-BUS output channel. Per-channel BER pattern; the pseudo random BER test pattern will be presented to the backplaneST-BUS output channel. Per-channel input. The backplane ST-BUS is input Reserved
.
001
010
011
100 101
110 111
BTM2
BTM1
BTM0
Input Source Local x x x x Backplane
Var. delay
Const. delay
Msg Mode
BER
Per Channel Input (HiZ)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
x x x x x x x Reserved
12- 8
BSAB4 - 0
Source Stream Address Bits: These five bits refer to the number of the data stream for the source (backplane or local) connection. Table 24 - Backplane Connection Memory Bits
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Zarlink Semiconductor Inc.
ZL50031
Bit 7-0 (See Note 1) Name BCAB7 - 0 Description
Data Sheet
Source Channel Address Bits: These eight bits refer to the number of the channel for the source (backplane or local) connection.
Note 1: Only Bits 7-0 will be used for per-channel message mode for the backplane BSTio streams. Table 24 - Backplane Connection Memory Bits (continued) (continued)
Data Rate 2 Mbps 4 Mbps 8 Mbps
Source Stream LSTi0-15 LSTi0-15 LSTi0-15
BSAB Bit Usage BSAB3-0 BSAB3-0 BSAB3-0
BCAB Bit Usage BCAB4-0 (32-ch/frame) BCAB5-0 (64-ch/frame) BCAB6-0 (128-ch/frame)
Table 25 - BSAB and BCAB Bits Usage when Source Streams are from the Local Port
Data Rate 8 Mbps 16 Mbps
Source Stream BSTio0-31 BSTio0-15
BSAB Bit Usage BSAB4-0 BSAB3-0
BCAB Bit Usage BCAB6-0 (128-ch/frame) BCAB7-0 (256-ch/frame)
Table 26 - BSAB and BCAB Bits Usage when Source Streams are from the Backplane Port
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Zarlink Semiconductor Inc.
ZL50031
15 LTM 2 14 LTM 1 13 LTM 0 12 LSAB 4 11 LSAB 3 10 LSAB 2 9 LSAB 1 8 LSAB 0 7 LCAB 7 6 LCAB 6 5 LCAB 5 4 LCAB 4 3 LCAB 3 2 LCAB 2
Data Sheet
1 LCAB 1
0 LCAB 0
Bit 15 -13
Name LTM2 - 0
Description Throughput Delay and Message Channel Control Bits: These three bits control the local ST-BUS output.
LTM2-0 000 Throughput Delay and Message Mode Control Per-channel variable delay from local interface; the content of the connection memory is the local data memory address of the switched input channel and stream. The local ST-BUS output is from local ST-BUS input. Per-channel constant delay from local interface; the content of the connection memory is the local data memory address of the switched input channel and stream. The local ST-BUS output is from local ST-BUS input. Per-channel variable delay from backplane interface; the content of the connection memory is the backplane data memory address of the switched input channel and stream. The local ST-BUS output is from the backplane CT-Bus input. Per-channel constant delay from the backplane interface; the content of the connection memory is the backplane data memory address of the switched input channel and stream. The local ST-BUS output is from backplane CT-Bus input. Per-channel message mode; only the lower byte (bits 7 to 0) of the connection memory location will be presented to the local ST-BUS output channel. Per-channel BER pattern; the pseudo random BER test pattern will be presented to the local ST-BUS output channel. Per-channel high impedance. The local ST-BUS output is high-impedance. Reserved
.
001
010
011
100 101
110 111
LTM2
LTM1
LTM0
Input Source Local x x x x Backplane
Var. delay x
Const. delay
Msg Mode
BER
Per Channel (HiZ)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
x x x x x x Reserved
12 - 8 7-0 (See Note 1)
LSAB4 LSAB0 LCAB7 LCAB0
Source Stream Address Bits: These five bits refer to the number of the data stream for the source (local or backplane) connection. Source Channel Address Bits: These eight bits refer to the number of the channel that is the source (local or backplane) connection.
Note 1: Only Bits 7-0 will be used for per-channel message mode for the local LSTo streams.
Table 27 - Local Connection Memory Bits
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Zarlink Semiconductor Inc.
ZL50031
Data Rate 8 Mbps 16 Mbps Source Stream BSTio0-31 BSTio0-15 LSAB Bit Usage LSAB4-0 LSAB3-0
Data Sheet
LCAB Bit Usage LCAB6-0 (128-ch/frame) LCAB7-0 (256-ch/frame)
Table 28 - LSAB and LCAB Bits Usage when Source Stream is from the Backplane Port
Data Rate 2 Mbps 4 Mbps 8 Mbps
Source Stream LSTi0-15 LSTi0-15 LSTi0-15
LSAB Bit Usage LSAB3-0 LSAB3-0 LSAB3-0
LCAB Bit Usage LCAB4-0 (32-ch/frame) LCAB5-0 (64-ch/frame) LCAB6-0 (128-ch/frame)
Table 29 - LSAB and LCAB Bits Usage when Source Stream is from the Local Port
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Zarlink Semiconductor Inc.
ZL50031
22.0 DC/AC Electrical Characteristics
Parameter 1 2 3 4 5 6 Supply Voltage BSTio Bias Voltage Input Voltage Output Voltage Package power dissipation Storage temperature Symbol VDD VDD5V VI Vo PD TS - 55 Min. -0.5 -0.5 -0.5 -0.5 Max. 5.0 7.0
Data Sheet
Absolute Maximum Ratings*
Units V V V V W C
VDD + 0.5 VDD + 0.5 2 +125
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 3 4 5 Operating Temperature Positive Supply BSTio Bias Voltage (3 V PCI Spec) BSTio Bias Voltage (5 V PCI Spec) Input Voltage Input Voltage on 5 V Tolerant Inputs Sym. TOP VDD VDD5V VDD5V VI VI_5V Min. -40 3.0 3.0 4.5 0 0 Typ. 25 3.3 3.3 5.0 Max. +85 3.6 3.6 5.5 VDD VDD5V Units C V V V V V
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to ground (Vss) unless otherwise stated.
Characteristics 1 2 3 4 Supply Current Input High Voltage Input Low Voltage Input Leakage (input pins) Sym. IDD VIH VIL IL 0.7VDD 0.3VDD 15 Min. Typ. Max. 480 Units mA V V A 0 < V < VDD_IO See Note 1 5 6 7 8 9 10 Weak Pullup Current Weak Pulldown Current Input Pin Capacitance Output High Voltage Output Low Voltage High Impedance Leakage IPU IPD CI VOH VOL IOZ 0.8VDD 0.4 5 33 33 5 50 50 10 A A pF V V A IOH = 10 mA IOL = 10 mA 0 < V < VDD_IO Input at 0V Input at VDD Test Conditions Outputs unloaded
11 Output Pin Capacitance CO 15 pF Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (Vin).
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Zarlink Semiconductor Inc.
ZL50031
Data Sheet
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
Characteristics 1 2 3 CMOS Threshold Rise/Fall Threshold Voltage High Rise/Fall Threshold Voltage Low Sym. VCT VHM VLM Level 0.5VDD 0.7VDD 0.3VDD Units V V V Conditions
AC Electrical Characteristics - Input Frame Pulse and Input Clock Timing Characteristic 1 2 3 4 5 6 7 FRAME_A_io, FRAME_B_io Input Frame Pulse Width FRAME_A_io, FRAME_B_io Input Frame Pulse Setup Time FRAME_A_io, FRAME_B_io Input Frame Pulse Hold Time C8_A_io, C8_B_io Input Clock Period C8_A_io, C8_B_io Input Clock High Time C8_A_io, C8_B_io Input Clock Low Time C8_A_io, C8_B_io Input Rise/Fall Time Sym. tCFPIW tCFPIS tCFPIH tC8MIP tC8MIH tC8MIL trC8i, tfC8i Min. 90 45 45 112 48 48 0 122 Typ. 122 Max. Units Notes 180 90 90 132 74 74 5 ns ns ns ns ns ns ns
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
FRAME_A_io, FRAME_B_io (INPUT) tCFPIS
CBFPIW
tBFPH tC8MIP tC8MIL tC8MIH
C8_A_io, C8_B_io (INPUT) Backplane Frame Boundary
trC8i
tfC8i
Figure 15 - Backplane Frame Pulse Input and Clock Input Timing Diagram
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Zarlink Semiconductor Inc.
ZL50031
AC Electrical Characteristics - Output Frame Pulse and Output Clock Timing Characteristic
1 2 3
Data Sheet
Sym.
tFBOS
Min. -6.25 114.5 57.25
Typ. 122
Max. 10 129.5 64.75
Units ns ns
Notes
Backplane Frame Boundary Offset FRAME_A_io, FRAME_B_io Output Pulse Width Delay from FRAME_A_io, FRAME_B_io output falling edge to C8_a_io,C8_B_io output rising edge Delay from C8_A_io,C8_B_io output rising edge to FRAME_A_io,FRAME_B_io output rising edge C8_A_io, C8_B_io Output Clock Period C8_A_io, C8_B_io Output High Time C8_A_io, C8_B_io Output Low Time C8_A_io, C8_B_io Output Rise Time C8_A_io, C8_B_io Output Fall Time C32/64o (32.768 MHz) Output Delay Time C32/64o (32.768 MHz) Period C32/64o (32.768 MHz) High Time C32/64o (32.768 MHz) Low Time C32/64o (65.536 MHz) Period C32/64o (65.536 MHz) High Time C32/64o (65.536 MHz) Low Time C32/64o Clock Rise Time (32.768 MHz or 65.536 MHz) C32/64o Clock Fall Time (32.768 MHz or 65.536 MHz)
tCFPOW tCFODF
CL=30 pF
ns
4
tCFODR
57.25
64.75
ns
5 6 7 8 9 10 11 12 13 14 15 16 17 18
tC8MP tC8MH tC8ML trC8o tfC8o tC32MOD tC32MP tC32MH tC32ML tC64MP tC64MH tC64ML tr32o tf32o
114.5 57.25 57.25
122
129.5 64.75 64.75 13 14 7.5
ns ns ns ns ns ns ns ns ns ns ns ns ns
CL=30 pF CL=30 pF
23 11.5 11.5 11.5 6.5 6.5
30.5
38 19 19 19 8 13 5 6
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
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Data Sheet
Backplane Frame Boundary tFBOS FRAME_A_io, FRAME_B_io (OUTPUT) tCFPOW
tCFODR C8_A_io, C8_B_io (OUTPUT) tC8MH tC8ML
tCFODF tC8MP
tC32ML tC32MH C32/64o (32.768 MHz) tC64ML C32/64o (65.536 MHz) tC64MH
trC8o tC32MP tC32MOD
tfC8o
tC64MP tC64MOD
trC32o
tfC32o
Figure 16 - Backplane Frame Pulse Output and Clock Output Timing Diagram (in Primary Master Mode and Secondary Master Mode) AC Electrical Characteristics - C20i Master Input Clock Timing Characteristic
1 2 3 4 5
Sym. tC20MP tC20MH tC20ML trC20M, tfC20M
Min. 49.995 -100 20 20
Typ. 50
Max. 50.005 100 30 30 10
Units ns ppm ns ns ns
Notes
C20i Input Clock Period C20i Input Clock Tolerance C20i Input Clock High Time C20i Input Clock Low Time C20i Input Rise/Fall Time
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
tC20MP tC20ML C20i trC20M tfC20M tC20MH
Figure 17 - Backplane Frame Pulse Input and Clock Input Timing Diagram
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Zarlink Semiconductor Inc.
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AC Electrical Characteristics - Reference Input Timing Characteristic 1 2 3 4 5 6 7 8 9 CTREF1, CTREF2, LREF0-3 Period CTREF1, CTREF2, LREF0-3 High Time CTREF1, CTREF2, LREF0-3 Low Time CTREF1, CTREF2, LREF0-3 Rise/Fall Time CTREF1, CTREF2, LREF0-3 Period CTREF1, CTREF2, LREF0-3 High Time CTREF1, CTREF2, LREF0-3 Low Time CTREF1, CTREF2, LREF0-3 Rise/Fall Time CTREF1, CTREF2, LREF0-3 Period Sym. tR8KP tR8kh tR8kL trR8K, tfR8K tR2MP tR2Mh tR2ML trR2M, tfR2M tR1M5P tR1M5h tR1M5L trR1M5, tfR1M5 Min. 121 0.09 0.09 0 366 90 90 0 486 90 90 0 648 324 324 488 244 244 Typ. 125 Max. 129 128.91 128.91 20 610 520 520 20 810 720 720 20 Units s s s ns ns ns ns ns
ns
Data Sheet
Notes 8 kHz Mode
2.048 MHz Mode
10 CTREF1, CTREF2, LREF0-3 High Time 11 CTREF1, CTREF2, LREF0-3 Low Time 12 CTREF1, CTREF2, LREF0-3 Rise/Fall Time
ns ns ns
1.544 MHz Mode
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
tR8KP CTREF1, CTREF2, LREF0-3 (8 kHz) tR8KH tR8KL
trR8K
tfR8K
Figure 18 - Reference Input Timing Diagram when the input frequency = 8 kHz
tR2MP CTREF1, CTREF2, LREF0-3 (2.048 MHz)
tR2ML
tR2MH
trR2M
tfR2M
Figure 19 - Reference Input Timing Diagram when the input frequency = 2.048 MHz
tR1M5P CTREF1, CTREF2, LREF0-3 (1.544 MHz)
tR1M5L
tR1M5H
trR1M5
tfR1M5
Figure 20 - Reference Input Timing Diagram when the input frequency = 1.544 Hz
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Zarlink Semiconductor Inc.
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AC Electrical Characteristics - Reference Output Timing Characteristic 1 NREFo Output Delay Time 2 NREFo Clock Period 3 NREFo Clock High Time 4 NREFo Clock Low Time 5 NREFo Clock Rise/Fall Time 6 NREFo Clock Period 7 NREFo Clock High Time 8 NREFo Clock Low Time 9 NREFo Clock High Time 10 NREFo Clock Low Time Sym. tROD tRP tRH tRL trREF, tfREF tR8KOP tR8KO2H tR8KO2L tR8KO15H tR8KO15L Same as LREF0-3 Period Same as LREF0-3 High Time Same as LREF0-3 Low Time 0 124.9 124.4 480.5 124.3 640.5 125 124.5 488 124.4 648 12 14 125.1 124.6 495.5 124.5 655.5 ns s s ns s ns Min. Typ. Max. 20 Units ns
Data Sheet
Notes
(DIV1,DIV0) = (0,0) in the DOM2 Register (DIV1,DIV0) = (0,1) or (DIV1,DIV0) = (1,0) in the DOM2 Register
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
LREF0-3 (8 kHz) NREFo (8 kHz)
tROD
tRP tRH tfREF
tRL
trREF
Figure 21 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register
LREF0-3 (2.048 MHz) NREFo (2.048 MHz)
tROD
tRP
tRL
tRH trREF tfREF
Figure 22 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register
LREF0-3 (1.544 MHz) NREFo (1.544 MHz)
tROD
tRP
tRL trREF
tRH tfREF
Figure 23 - Reference Input Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register
LREF0-3 (2.048 MHz) NREFo (8 kHz)
tROD tR8KO2L trREF tfREF
tR8KOP
tR8KO2H
Figure 24 - Reference Output Timing Diagram when (DIV1, DIV0) = (1, 0) in DOM2 Register
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Zarlink Semiconductor Inc.
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Data Sheet
LREF0-3 (1.544 MHz) NREFo (8 kHz)
tROD tR8KO15L trREF tfREF
tR8KOP
tR8KO15H
Figure 25 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 1) in DOM2 Register AC Electrical Characteristics - Local Frame Pulse and Clock Timing, ST_CKo = 4.096 MHz Characteristic 1 2 3 4 5 6 7 8 Local Frame Boundary Offset1 ST_FPo0/1 Width ST_FPo0/1 Output Delay from Falling edge of ST_FPo0/1 to falling edge of ST_CKo0/1 ST_FPo 0/1Output Delay from Falling edge of ST_CKo0/1 to rising edge of ST_FPo0/1 ST_CKo0/1 Clock Period ST_CKo0/1 Clock Pulse Width High ST_CKo0/1 Clock Pulse Width Low ST_CKo0/1 Clock Rise/Fall Time tCP4 tCH4 tCL4 trC4o, tC4o 236.5 118.3 118.3 244 251.5 125.8 125.8 14 ns ns ns ns Sym. tLFBOS tFPW4 tFODF4 tFODR4 Min. 6.5 236.5 118.3 118.3 244 Typ. Max. 25 251.5 125.8 125.8 Units ns ns ns CL=30 pF ns Notes
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. Note 1: No jitter presented on input reference clock.
Backplane Frame Boundary
Local Output Frame Boundary tLFBOS
tFPW4 ST_FPo0/1 tFODF4 tCP4 tCH4 ST_CKo0/1 (4.096 MHz) tfC4o trC4o tCL4 tFODR4
Figure 26 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 4.096 MHz
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Zarlink Semiconductor Inc.
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Data Sheet
AC Electrical Characteristics - Local Frame Pulse and Clock Timing, ST_CKo0 = 8.192 MHz Characteristic 1 2 3 4 5 6 7 8 Local Frame Boundary Offset1 ST_FPo0/1 Width ST_FPo0/1 Output Delay from Falling edge of ST_FPo0/1 to falling edge of ST_CKo0/1 ST_FPo0/1 Output Delay from Falling edge of ST_CKo0-1 to rising edge of ST_FPo0/1 ST_CKo0/1 Clock Period ST_CKo0/1 Clock Pulse Width High ST_CKo0/1 Clock Pulse Width Low ST_CKo0/1 Clock Rise/Fall Time Sym. tLFBOS tFPW8 tFODF8 tFODR8 tCP8 tCh8 tCL8 trC8o, tfC8o Min. 6.5 114.5 57.3 57.3 114.5 57.3 57.3 122 122 Typ. Max. 25 129.5 64.8 64.8 129.5 64.8 64.8 14 Units ns ns ns ns ns ns ns ns CL=30 pF Notes
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. Note 1: No jitter presented on input reference clock.
Backplane Frame Boundary
Local Output Frame Boundary tLFBOS
tFPW8 ST_FPo0/1 tFODF8 tCL8 ST_CKo0/1 (8.192 MHz) tCH8 tFODR8 tCP8
trC8o
tfC8o
Figure 27 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 8.192 MHz
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Zarlink Semiconductor Inc.
ZL50031
AC Electrical Characteristics - Local Frame Pulse and Clock Timing, ST_CKo = 16.384 MHz Characteristic 1 2 3 Local Frame Boundary Offset1 ST_FPo0/1 Width ST_FPo0/1 Output Setup from Falling edge of ST_FPo0/1 to falling edge of ST_CKo0/1 ST_FPo Output Hold from Falling edge of ST_CKo0/1 to rising edge of ST_FPo0/1 5 6 7 8 ST_CKo0/1 Clock Period ST_CKo0/1 Clock Pulse Width High ST_CKo0/1 Clock Pulse Width Low ST_CKo0/1 Clock Rise/Fall Time tCP16 tCh16 tCL16 trC16o, tfC16o 53.5 26.8 26.8 61 68.5 34.3 34.3 15 ns ns ns ns Sym. tLFBOS tFPw16 tFODF16 Min. 6.5 53.5 26.8 61 Typ. Max. 24.5 68.5 34.3 Units ns ns ns
Data Sheet
Notes
4
tFODR16
26.8
34.3
ns CL=30 pF
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. Note 1: No jitter presented on input reference clock.
Backplane Frame Boundary tLFBOS tFPW16
Local Output Frame Boundary
ST_FPo0/1
tFODF16 tCL16 tCH16 tFODR16 tCP16
ST_CKo0/1
(16.384 MHz) trC16o tfC16o
Figure 28 - Local Clock Timing Diagram when ST_CKo frequency = 16.384 MHz
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Zarlink Semiconductor Inc.
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AC Electrical Characteristics- C1M5o Output Clock Timing
Characteristic 1 2 3 4 5 C1M5o Period C1M5o High Time C1M5o Low Time C1M5o Rise Time C1M5o Fall Time Sym. tC1M5oP tC1M5oH tC1M5oL trC1M5o tfC1M5o Min. 640.5 320.2 320.2 Typ. 648 324 324 Max. 655.5 327.8 327.8 10 11
Data Sheet
Units ns ns ns ns ns
Notes
CL=30 pF
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
C1M5o (1.544MHz) trC1M5o tC1M5oL tC1M5oP tC1M5oH tfC1M5o
Figure 29 - C1M5o Output Clock Timing Diagram
AC Electrical Characteristics- Output Clock Jitter Generation (Unfiltered)
Characteristic 1 2 3 4 Jitter at C1M5o (1.544 MHz) Jitter at ST_CKo0-1 (4.096 MHz) Jitter at ST_CKo0-1 (8.192 MHz) Jitter at ST_CKo0-1 (16.384 MHz) Typ. 7.4 7.1 7.0 7.6 Max. 8.0 8.8 8.3 9.9 Units ns-pp ns-pp ns-pp ns-pp Notes
Device locks to1.544 MHZ reference input, and no jitter present on the reference
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
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Zarlink Semiconductor Inc.
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AC Electrical Characteristics - Backplane Serial Streams with Date Rate of 8 Mbps Characteristic 1 2 3 4 5 BSTio0-31 Input Data Sample Point BSTio0-31 Input Setup Time BSTio0-31 Input Hold Time BSTio0-31 Output Delay Active to Active Per Channel boundary HiZ Sym. tSAMP8 tCIS8 tCIH8 tDOD8 tDOZ8 tZDO8 Min. 91.5 12.5 12.5 -6.5 10 10 12.5 Typ. 91.5 Max. 91.5 Units ns ns ns ns ns ns
Data Sheet
Test Conditions
CL = 30 pF, Note 1 RL=1 K, CL=30 pF, Note 2
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * Note 1: To meet the H.110 output timing requirement, the output delay time can be reduced further by programming the backplane output advancement registers (BOA0 - 3). * Note 2: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel the time taken to discharge C L.
FRAME_A_io, FRAME_B_io (INPUT) C8_A_io, C8_B_io (8.192 MHz) (INPUT) BSTio (8 Mbps) Backplane input
Bit 6 Ch127
tSAMP8 tCIS8
Bit 7 Ch127 Bit 0 Ch 0
tCIH8
Bit 1 Ch 0 Bit 2 Ch 0 Bit 3 Ch 0 Bit 4 Ch 0
VTT
tZDO8
tDOD8
Bit 0 Ch 0 Bit 1 Ch 0 Bit 2 Ch 0 Bit 3 Ch 0 Bit 4 Ch 0
BSTio (8 Mbps) Backplane output
Bit 6 Ch127
Bit 7 Ch127
VTT
tDOZ8
Figure 30 - Backplane Serial Stream Timing when the Data Rate is 8 Mbps
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Zarlink Semiconductor Inc.
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AC Electrical Characteristics - Backplane Serial Streams with Date Rate of 16 Mbps Characteristic 1 2 3 4 BSTio0-15 Input Data Sample Point BSTio0-15 Input Setup Time BSTio0-15 Input Hold Time BSTio0-15 Output Delay Active to Active Sym. tSAMP16 tCIS16 tCIH16 tDOD16 Min. 46 12.5 12.5 -6.5 12.5 Typ. 46 Max. 46 Units ns ns ns ns
Data Sheet
Test Conditions
CL = 30 pF
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
FRAME_A_io, FRAME_B_io C8_A_io, C8_B_io (8.192 MHz)
tCIS16
tSAMP16 tCIH16
Bit 7 Ch 0 Bit 6 Ch 0 Bit 5 Ch 0 Bit 4 Ch 0 Bit 3 Ch 0 Bit 2 Ch 0 Bit 1 Ch 0 Bit 0 Ch 0 Bit 7 Ch 1 Bit 6 Ch 1
BSTio (16 Mbps) Backplane input
Bit 3 Ch255
Bit 1 Bit 2 Ch255 Ch255
Bit 0 Ch255
VTT
tDOD16
BSTio (16 Mbps) Backplane output
Bit 3 Ch255
Bit 1 Bit 2 Ch255 Ch255
Bit 0 Ch255
Bit 7 Ch 0
Bit 6 Ch 0
Bit 5 Ch 0
Bit 4 Ch 0
Bit 3 Ch 0
Bit 2 Ch 0
Bit 1 Ch 0
Bit 0 Ch 0
Bit 7 Ch 1
Bit 6 Ch 1
VTT
Figure 31 - Backplane Serial Stream Timing when the Data Rate is 16 Mbps
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Zarlink Semiconductor Inc.
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AC Electrical Characteristics - Local Serial Stream Output Timing Characteristic 1 LSTo Delay - Active to Active @2.048 Mbps @4.096 Mbps @8.192 Mbps Sym. tSOD2 tSOD4 tSOD8 Min. -17.5 -17.5 -17.5 Typ. Max. -6 -6 -6 Units ns ns ns
Data Sheet
Test Conditions CL = 30 pF CL = 30 pF CL = 30 pF
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * See Section 7.0, "Local Output Timing Considerations" on page 15
ST_FPo0/1, ST_CKo0/1
tSOD8
LSTo (8 Mbps) Local output
Bit 1 Ch127
Bit 0 Ch127
Bit 7 Ch 0
Bit 6 Ch 0
Bit 5 Ch 0
Bit 4 Ch 0
Bit 3 Ch 0
Bit 2 Ch 0
VTT
tSOD4
LSTo (4 Mbps) Local output
Bit 7, Ch 0
Bit 6, Ch 0
Bit 5, Ch 0
VTT
tSOD2
LSTo (2 Mbps) Local output
Bit 0, Ch 31
Bit 7, Ch 0
Bit 6, Ch 0
VTT
Figure 32 - Local Serial Stream Output Timing
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Zarlink Semiconductor Inc.
ZL50031
AC Electrical Characteristics - Local Serial Stream Input Timing Characteristic 1 LSTi Input Data Sample Point @2.048 Mbps @4.096 Mbps @8.192 Mbps LSTi Setup Time @2.048 Mbps @4.096 Mbps @8.192 Mbps LSTi Hold Time @2.048 Mbps @4.096 Mbps @8.192 Mbps Sym. tSAMP2L tSAMP4L tSAMP8L tSIS2 tSIS4 tSIS8 tSIH2 tSIH4 tSHI8 Min. 366 183 91.5 12.5 12.5 12.5 12.5 12.5 12.5 Typ. 366 183 91.5 Max. 366 183 91.5 Units ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions
2
3
ST_FPo0/1, ST_CKo0/1
tSAMP8 tSIS8 tSIH8
Bit 7 Ch 0 Bit 6 Ch 0 Bit 5 Ch 0 Bit 4 Ch 0 Bit 3 Ch 0
LSTi (8 Mbps) Local input
Bit 1 Ch 0
Bit 0 Ch 0
VTT
tSAMP4
tSIS4
Bit 7 Ch 0
tSIH4
Bit 6 Ch 0
LSTi (4 Mbps) Local input
tSAMP2
Bit 0 Ch63
VTT
tSIS2
Bit 7 Ch 0
tSIH2
LSTi (2 Mbps) Local input
Bit 0 Ch31
VTT
Figure 33 - Local Serial Stream Input Timing
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Zarlink Semiconductor Inc.
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AC Electrical Characteristics - Local and Backplane Tristate Timing Characteristic 1 LSTo/BSTio Delay - Active to High-Z - High-Z to Active 2.048 Mbps (local) 4.096 Mbps (local) 8.192 Mbps (local) 8.192 Mbps (backplane) 16.384 Mbps (backplane) 2 Output Driver Enable (ODE) Delay - High-Z to Active 2.048 Mbps (local) 4.096 Mbps (local) 8.192 Mbps (local) 8.192 Mbps (backplane) 16.384 Mbps (backplane) Output Driver Disable (ODE) Delay - Active to High-Z 2.048 Mbps (local) 4.096 Mbps (local) 8.192 Mbps (local) 8.192 Mbps (backplane) 16.384 Mbps (backplane) Sym. tDZ, tZD Min. Typ. Max. Units
Data Sheet
Test Conditions
-19.5 -19.5 -19.5 -8.5 -8.5
-4 -4 -4 14.5 14.5
ns ns ns ns ns
RL=1 K, CL=30 pF, See Note 1.
tZD_ODE
37 37 37 20 20
ns ns ns ns ns
2
tDZ_ODE
20 20 20 20 20
ns ns ns ns ns
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * Note 1: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel the time taken to discharge C L.
ST_CKo0/1 (Output)
VTT tDZ Valid Data tZD Tri-state VTT
LSTo/BSTio
LSTo/BSTio
Tri-state
Valid Data
VTT
Figure 34 - Serial Output and External Control
C8_A_io C8_B_io (Input)
VTT tDZ Valid Data tZD Tri-state Valid Data VTT Tri-state VTT
LSTo/BSTio (Output)
LSTo/BSTio (Output)
Figure 35 - Serial Output and External Control
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Zarlink Semiconductor Inc.
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Data Sheet
ODE tZD_ODE LSTo/BSTio (Output) HiZ Valid Data tDZ_ODE HiZ
VTT
VTT
Figure 36 - Output Driver Enable (ODE)
AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode Characteristics 1 2 3 4 5 6 7 8 9 11 CS setup from DS falling R/W setup from DS falling Address setup from DS falling CS hold after DS rising R/W hold after DS rising Address hold after DS rising Data setup from DTA Low on Read Data hold on read Valid Write Data Setup Acknowledgment Delay: Reading/Writing Registers Reading/Writing Memory Sym. tCSS tRWS tADS tCSH tRWH tADH tDDR tDHR tWDS tDHW tAKD 8 97/82 110/95 158/114 171/127 30 Min. 0 15 5 0 0 5 20 20 20 Typ. Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns CL=30 pF CL=30 pF CL=30 pF, RL=1 K, See Note 2 CL=30 pF CL=30 pF, RL=1 K See Note 2 Test Conditions1
10 Data hold on write
12 Acknowledgment Hold Time
tAKH
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. *Note 1: A delay of 100 microseconds must be applied before the first microprocessor access is performed after the RESET pin is set high. *Note 2: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel the time taken to discharge C L.
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Zarlink Semiconductor Inc.
ZL50031
Data Sheet
DS tCSS CS tRWS R/W tADS A0-A13
VALID ADDRESS
VTT tCSH VTT tRWH VTT tADH VTT tDHR
D0-D15 READ tWDS D0-D15 WRITE
VALID READ DATA
VTT tDHW
VALID WRITE DATA
VTT
tDDR DTA tAKD tAKH VTT
Figure 37 - Motorola Non-Multiplexed Bus Timing AC Electrical Characteristics - JTAG Test Port and Reset Pin Timing Characteristic 1 2 3 4 5 6 7 8 9 TCK Clock Period TCK Clock Pulse Width High TCK Clock Pulse Width Low TMS Set-up Time TMS Hold Time TDi Input Set-up Time TDi Input Hold Time TDo Output Delay TRST pulse width Sym. tTCKP tTCKH tTCKL tTMSS tTMSH tTDIS tTDIH tTDOD tTRSTW tRSTW 20 400 Min. 200 80 80 10 10 20 20 30 Typ. Max. Units ns ns ns ns ns ns ns ns ns ns CL=30 pF CL=30 pF CL=30 pF Notes
10 Reset pulse width
Characteristics are over recommended operating conditions unless otherwise stated.
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Zarlink Semiconductor Inc.
ZL50031
tTCKL TCK tTCKH tTCKP
Data Sheet
tTMSS TMS
tTMSH
tTDIS tTDIH TDi tTDOD TDo tTRSTW TRST
Figure 38 - JTAG Test Port Timing Diagram
tRSTW Reset
Figure 39 - Reset Pin Timing Diagram
23.0
Trademarks
CompactPCI(R) is a registered trademark of PICMG-PCI Industrial Computer Manufacturers Group, Inc.
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Zarlink Semiconductor Inc.
For more information about all Zarlink products visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved.
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